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3-6-1 DRAM Timing Control
CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
DRAM Timing Control
Item Help
Memory Timing Parameter Auto
Current CAS Latency
Current TRCD
Current TRP
Current TRAS
x Manual CAS Latency 2.5 Clocks
x Manual TRCD 3 Clocks
x
Manual
TRP
3
Clocks
x Manual TRAS
7 Clocks
Memory I/F Timing Auto
Memory Dynamic CKE
Disabled
Memory Read Bypass
Disabled
Memory Async Mode
Disabled
Menu Level >>
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Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Manual CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the
DRAM timing. The settings are: 2T and 2.5T.
Manual TRCD/ Manual TRP
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before DRAM
refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast gives faster
performance; and Slow gives more stable performance. This field applies only when
synchronous DRAM is installed in the system. The settings are: 2T, 3T and 4T.
Manual TRAS
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 6T, 7T and 8T.
