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SDRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
3-7 Integrated Peripherals
CMOS Setup Utility – Copyright(C) 1984-2002 Award Software
Integrated Peripherals
Item Help
> OnChip IDE Function Press Enter
> OnChip Device Function Press Enter
> Onboard Super IO Function Press Enter
Init Display First PCI Slot
Menu Level >
↑ ↓ → ←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
OnChip IDE Function
Please refer to section 3-7-1
OnChip Device Function
Please refer to section 3-7-2
Onboard Super IO Function
Please refer to section 3-7-3
Init Display First
This item allows you to decide to activate whether PCI Slot or AGP VGA first. The settings
are: PCI Slot, AGP Slot.
3-7-1 OnChip IDE Function
CMOS Setup Utility – Copyright(C) 1984-2002 Award Software
OnChip IDE Function
Internal PCI/IDE Both
Primary Master PIO Auto
Item Help