PCI Timing Setting Press Enter
Select Display Device CRT
TV-Type NTSC
TV-Connector CVBS
System BIOS Cacheable Disabled
Video RAM Cacheable Enabled
Memory Parity/ECC Check Disabled
Memory Size Hole Disabled
Menu Level >
Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Note: Change these settings only if you are familiar with the chipset.
DRAM Timing Setting
Please refer to section 3-6-1
AGP Timing Setting
Please refer to section 3-6-2
PCI Timing Setting
Please refer to section 3-6-3
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video BIOS Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
3-6-1 DRAM Timing Setting
CMOS Setup Utility – Copyright(C) 1984-2003 Award Software
DRAM Timing Setting
DRAM Timing By SPD
x DRAM CAS Latency 2.5
Bank Interleave 4 Banks
RAS Precharge Time 3T
RAS Active Time 6T
Item Help
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27
