Inputs and Outputs
ADwin
14
ADwin-Gold
USB / ENET, manual version 3.8, October 2005
Tolerance Ranges
Slight variations regarding the calculated values may be within the tolerance
range of the individual component. Two kinds of variations are possible (in
LSB), which are indicated in this hardware manual:
INL
– The integral non-linearity (INL) defines the maximum deviation from the
ideal straight line over the whole input voltage range.
DNL
– The differential non-linearity (DNL) defines the maximum deviation from
the ideal quantization level.
5.2 Digital Inputs and Outputs
Digital inputs/outputs
On two 25-pin D-SUB sockets (DIO 00…DIO 31) there are 32 digital inputs or
outputs. They are programmable in groups of 8 as inputs or outputs.
The digital inputs are TTL-compatible and not protected against over voltage.
Do not use pins marked as "reserved". They are planned for changes and
expansions and can cause damages to your system if you do not pay attention
to this fact.
Trigger input (EVENT)
The
ADwin-Gold
is equipped with an external trigger input (EVENT). With this
trigger input processes are triggered by an external signal (trigger) with rising
edge and can completely and immediately be processed, (see also
ADbasic
manual, chapter: "Program Structure").
Power-up configuration
After power-up of the device, all connections are configured as inputs.
CONF_DIO(12)
The instruction
CONF_DIO(12)
configures DIO 15:00 as digital inputs and
DIO 31:16 as digital outputs (see Fig. 10).
Only in this configuration will you be able to totally access the inputs and out-
puts with the instructions
DIGIN
,
DIGIN_WORD
,
DIGOUT_WORD
,
SET_DIGOUT
,
CLEAR_DIGOUT
.
About programming under other configurations the following chapter will give
you more detailed information: chapter 5.3 "Time-Critical Tasks" (see also
ADbasic
manual and tutorial).
Fig. 10 – Pin assignment with the configuration
CONF_DIO(12)
5.3 Time-Critical Tasks
For extremely time-critical tasks you can use instructions with which you have
direct access to the
control and data registers of the ADC and DAC
(see
ADbasic
manual). These registers can be found in the memory address area
of the ADSP (memory mapped). These instructions also allow to optimize the
program structure (s.b.).
Inputs / DIGIN
Outputs / DIGOUT
CONN. 1
(male)
13
12
11
10
9
8
7
6
5
4
3
2
1
25
24
23
22
21
20
19
18
17
16
15
14
DI
GI
N-00
DI
GI
N-02
DI
GI
N-04
DI
GI
N-06
DI
GI
N-08
DI
GI
N-10
DI
GI
N-12
DI
GI
N-14
EVEN
T
GND
DI
GI
N-01
DI
GI
N-03
DI
GI
N-05
DI
GI
N-07
DI
GI
N-09
DI
GI
N-11
DI
GI
N-13
DI
GI
N-15
GND
R
ESER
VED
R
ESER
VED
CONN. 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
+5V
(out
put
, max.
0.
1A
)
DI
GOUT-14
DI
GOUT-12
DI
GOUT-10
DI
GOUT-08
DI
GOUT-06
DI
GOUT-04
DI
GOUT-02
DI
GOUT-00
GND
DI
GOUT-15
DI
GOUT-13
DI
GOUT-11
DI
GOUT-09
DI
GOUT-07
DI
GOUT-05
DI
GOUT-03
DI
GOUT-01
R
ESER
VED
R
ESER
VED
