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LTE-Lite User Manual

2.3.5 SMT Module Power Connection

The LTE-Lite SMT Module is powered by an ex3.3V power supply with -0.15V and +0.25V
range on pins 21 and 22 of the module. The module typically draws less then 60mA of current. The
module also supplies pin 20 for antenna power biasing, and this pin is typically connected to the
ex3.3V power supply or it may be alternatively connected to 5V power supplies for 5V
antenna systems. All three power pins are internally bypassed for noise-filtering.
The module generates a low-noise, low-pass-filtered 3.0V internal power rail for the TCXO, DAC’s
and other sensitive circuits, and this power rail is available on pin 10 of the module for optional
additional bypassing and powering external circuitry such as optional external TCXO’s or buffer IC’s
with a low-noise 3.0V power rail. No noise should be injected into this power rail as that may
adversely affect the RF signal quality. The 3.0V output may source up to 50mA.

2.3.6 SMT Module Antenna Connection

The LTE-Lite SMT Module has an internal U.Fl coax antenna connector that is connected in parallel
to pin 18 of the module to allow for external antenna connections. Either the internal coax connector
or the external antenna feed from the users’ PCB can be used, but not both simultaneously. The
antenna input pin carries DC power that can be supplied from pin 20 of the module, is internally
RF-blocked and bypassed to the antenna power-pin 20, can support up to 100mA current, and
antenna voltage ranges of 3.0V to 5V. The unit supports external passive antennae (0dB gain) or
active antennae with up to +30dB antenna amplification at GPS L1 frequencies.

2.3.7 1PPS Module outputs

The LTE-Lite SMT Module provides a GPS raw 1PPS CMOS pulse on pin 15 with sawtooth present,
and a clean TCXO-generated, sawtooth-removed, UTC(GPS) phase-locked 1PPS output on pin 4.
Both outputs have 3.3V CMOS level, and are rising-edge aligned to UTC(GPS). The loop software
on the module will steer (discipline) the TCXO to become phase-locked to the raw GPS 1PPS output
signal, and thus the two 1PPS signals slowly converge upon each other. The process of slowly
phase-locking the clean 1PPS output to the raw GPS receiver 1PPS output can take several hours to
settle due to the long time-constants used in the phase locked loop, and may be disturbed by thermal
changes, airflow, tilt, acceleration, or vibration affecting the TCXO crystal frequency.

2.3.8 Synthesized RF Output Frequency

The LTE-Lite SMT Module contains an n/m RF synthesizer that uses the TCXO as a reference clock.
Thus frequencies that are multiples or integer fractions of the TCXO frequency may be generated and
output on the 3.3V CMOS RF output pin 24. This pin is not buffered, and can supply only up to
10mA of output current.

PLEASE NOTE THAT THE SYNTHESIZED OUTPUT PIN 24 IS ALSO USED AS THE
ISP#-ENABLE PIN DURING AND AFTER SYSTEM RESET, AND THIS PIN MUST THUS
NOT BE PULLED-LOW DURING RESET OTHERWISE THE BOARD WILL NOT
FUNCTION PROPERLY. THE SYNTHESIZED RF OUTPUT PIN 24 SHOULD THUS BE
BUFFERED BY A CMOS HIGH-IMPEDANCE-INPUT GATE WITHOUT ANY
PULL-DOWN RESISTORS IN THE CIRCUITRY.