39
3.5.17 SDRAM RAS-to-CAS Delay
This field specifies the delay in assertion of CAS# from the assertion of RAS# of SDRAM
memory. This is for the experienced users only.
Options
Description
Slow (*)
3 system clocks delay
Fast
2 system clocks delay
3.5.18 SDRAM RAS Precharge Time
This field specifies the SDRAM RAS# pre-charge requirements. This is for experienced users
only.
Options
Description
Fast (*)
2 system clocks for RAS# precharge
Slow
3 system clocks for RAS# precharge
3.5.19 SDRAM CAS Latency Time
This field specifies the SDRAM CAS latency timing parameter (the time from CAS# assertion to
data valid). This is for experienced users only.
Options
Description
2
2 system clocks
3 (*)
3 system clocks
3.5.20 Passive Release
When enabled, the south bridge PIIX4 will support the Passive Release mechanism when it is a
PCI master. The PCI revision 2.1 compliant requires this field to be enabled. This field is for
experienced users only.
Options
Enabled (*)
Disabled
3.5.21 Delayed Transaction
When enabled, the south bridge PIIX4 will supports the Delayed Transaction mechanism when it
is the target of a PCI transaction. The PCI revision 2.1 compliant requires this field to be enabled.
This field is for experienced users only.
Options
Enabled (*)
Disabled
