Standard Event Status Group
These registers are programmed by Common commands. The group consists
of an Event and Enable register. The Standard Event event register latches
events relating to communication status. It is a read-only register that is cleared
when read. The Standard Event enable register functions similarly to the enable
registers of the Operation and Questionable status groups.
Status Byte Register
This register summarizes the information from all other status groups as defined
in the IEEE 488.2 Standard Digital Interface for Programmable Instrumentation.
Master Status Summary and Request for Service Bits
MSS is a real-time (unlatched) summary of all Status Byte register bits that are
enabled by the Service Request Enable register. MSS is set whenever the in-
strument has one or more reasons for requesting service.
*STB?
reads the
MSS in bit position 6 of the response but does not clear any of the bits in the
Status Byte register.
The RQS bit is a latched version of the MSS bit. Whenever the instrument re-
quests service, it sets the SRQ interrupt line true and latches RQS into bit 6 of
the Status Byte register. When the controller does a serial poll, RQS is cleared
inside the register and returned in bit position 6 of the response. The remaining
bits of the Status Byte register are not disturbed.
Error and Output Queues
The Error Queue is a first-in, first-out (FIFO) data register that stores numerical
and textual description of an error or event. Error messages are stored until they
are read with
SYSTem:ERRor?
. If the queue overflows, the last error/event in
the queue is replaced with error -350, "Queue overflow".
The Output Queue is a first-in, first-out (FIFO) data register that stores mes-
sages until the controller reads them.
Bit Assignments
Questionable Status Register
Mnemonic
Bit
Value Bit Weight
Meaning
OV
0
1
Overvoltage
Protection
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