IRT DDC-3471 Instruction Manual Download Page 4

3471-ddc.ib.rev2.doc 

page 4 of 20

 17/10/2007

 

 

Applications: 

• 

Block length indication and error detection. 

• 

Interface to test equipment. 

• 

Interfacing to Telecoms switched data network. 

• 

Interfacing various MPEG2 TS formats. 

• 

Interleaving or de-interleaving. * 

• 

Reed Solomon insertion & correction. * 

• 

Spectrum dispersion correction. * 

• 

Signal monitoring for remote alarm indications.

  

 

*  DDC-3471 only. 

 
 

Application 

 
Processes which may be performed by the DDC-3471 are: 
 

Baseband interfacing and sync 

This unit adapts the data structure to the format of the signal source. This may be a DDC-3460 or simply the input 
interface of the DDC-3471. The framing structure is in accordance with MPEG-2 transport layer including sync 
Bytes. 
 

Sync 1 inversion and randomisation

 (Scrambling) 

The Sync 1 Byte is inverted according to the MPEG-2 framing structure, and the data stream randomised for 
spectrum shaping purposes. 
 

Reed-Solomon (RS) encoder 

A shortened Reed-Solomon (RS) code is applied to each randomised transport packet to generate an error-protected 
packet. This code is also applied to the Sync Byte itself. 
 

Convolutional interleaver 

This part performs a depth I = 12 convolutional interleaving of the error-protected packets. The periodicity of the 
sync Bytes remains unchanged. 
 

Block diagram 

 
 
 
 

 

DDC-3471 

Scrambling 

Reed-Solomon 

Insert 

Convolutional 

Interleaver 

Alarms & Indications 

SCRAMBLED 
RS PRESENT 
188 BYTE BLOCK 
204 BYTE BLOCK 
SYNC ERROR 
INPUT LOSS 

RS ERROR

Convolutional 
De-Interleaver 

Reed-Solomon 

Correction 

De-S

crambling 

LVDS 

 

NRZ

NRZ

 

LVDS 

8B

 

10B 

Input 

(270 Mb/s) coax

SPI 

 

SPI 

ASI-C 

Outputs 

IRT 

Communications 

www.irtcommunications.com

Summary of Contents for DDC-3471

Page 1: ...nd on the Internet at http www irtelectronics com I R T Electronics Pty Ltd A B N 35 000 832 575 26 Hotham Parade ARTARMON N S W 2064 AUSTRALIA National Phone 02 9439 3744 Fax 02 9439 7439 Internation...

Page 2: ...tallation in frame or chassis 8 Connections 9 Front rear panel connector diagrams 9 Operation 10 Front indicators 10 Processing controls 10 Maintenance storage 11 Warranty service 11 Equipment return...

Page 3: ...ts lower processing speed requirements The ASI O interface is of limited usefulness due to the specification of multimode fibre with only a short haul capability Optical transport of ASI can be better...

Page 4: ...randomisation Scrambling The Sync 1 Byte is inverted according to the MPEG 2 framing structure and the data stream randomised for spectrum shaping purposes Reed Solomon RS encoder A shortened Reed Sol...

Page 5: ...Temperature range 0 50 C ambient Mechanical Mounts in IRT FRU 1030 1 RU 19 rack chassis with input output and power connections on the rear panel Finish Front panel Grey enamel silk screened black let...

Page 6: ...ith the interleaver and RS encoder enabled SPI Output The SPI output uses differential LVDS signalling with a standard 25 pin D female connector The output is disabled when Input Loss Alarm is trigger...

Page 7: ...MPEG TS will be disturbed The time taken before normal decoding resumes is dependent on the decoder in use and may be up to five seconds LK 1 OUT Standard Operation IN Sets transport stream indicator...

Page 8: ...utions should be observed Where individual circuit cards are stored they should be placed in antistatic bags Proper antistatic procedures should be followed when inserting or removing cards from these...

Page 9: ...ata 3 B 8 Data 2 A 21 Data 2 B 9 Data l A 22 Data 1 B 10 Data 0 A 23 Data 0 B 11 DVALID A 24 DVALID B 12 PSYNC A 25 PSYNC B 13 Cable Shield Alarm connections J 1 Alarm relay output Front rear panel co...

Page 10: ...different MPEG TS formats In this context the word scrambling refers to the process of Sync1 inversion and randomisation for the purpose of energy dispersal of the signal It does not refer to the enc...

Page 11: ...inable from the component supplier Equipment return Before arranging service ensure that the fault is in the unit to be serviced and not in associated equipment If possible confirm this by substitutio...

Page 12: ...ta transfer is synchronised to the Byte clock of the MPEG transport stream The data to be transmitted are MPEG 2 transport packets The data signals are synchronised to the clock depending on the trans...

Page 13: ...rial data stream The disparity characteristics of the code maintain DC balance Special characters are defined as extra code points beyond the need to encode a Byte of data One in particular is used to...

Page 14: ...e PRBS registers is initiated at the start of every eight transport packets To provide an initialisation signal for the de scrambler the MPEG 2 sync Byte of the first transport packet in a group of ei...

Page 15: ...Byte stream by the input switch Each branch is a First In First Out FIFO shift register with depth Mj cells where M 17 N I N 204 error protected frame length I 12 interleaving depth branch index The c...

Page 16: ...dB Electrical characteristics CCITT G 703 34368 Kb s Cable type Coaxial Impedance 75 Signal level 1 0 V Nominal pulse width 14 55 ns Code conversion HDB3 Pulse shape Fig 17 G 703 Jitter at input port...

Page 17: ...simplifying system design Note that the ASI signal is polarity sensitive Although most 270 Mb s SDI DA s and switchers will pass ASI signals the line drivers used usually have both inverted and non i...

Page 18: ...11 12 GHz satellite services ETS 300 429 Digital broadcasting systems for Television sound and data services framing structure channel coding and modulation for cable systems ETS 300 473 Digital broad...

Page 19: ...U CCITT recommendation G 703 HDB3 High Density Bi polar of order 3 IF Intermediate Frequency IRD Integrated Receiver Decoder ITU International Telecommunications Union LSB Least Significant Bit LVDS L...

Page 20: ...10 2007 Drawing index Drawing Sheet Description 804489 1 DDC 3471 circuit schematic 804489 2 DDC 3471 circuit schematic 804489 3 DDC 3471 circuit schematic I R T C o m m u n i c a t i o n s w w w i r...

Page 21: ...SPI_OUT1 SPI_OUT2 SPI_OUT3 SPI_OUT4 SPI_OUT5 SPI_OUT6 SPI_OUT7 SPI_ENA SPI_CLK PCLK_IN SPI_IN0 SPI_IN1 SPI_IN2 SPI_IN3 SPI_IN4 SPI_IN5 SPI_IN6 SPI_IN7 RELSW RELCOM ASIOUT PS1 PS3 PS2 PS4 INENA SPI IN...

Page 22: ...22B 23A 23B 24A 24B 25A 25B 26A 26B 27A 27B 28A 28B 29A 29B 30A 30B 31A 31B 32A 32B M1 M2 PL2 DIN64M VCC GND VCC GND VCC GND SPI_ENA SPI_ENA SPI_ENA SPI_OUT1 SPI_OUT0 SPI_OUT3 SPI_OUT2 SPI_OUT4 SPI_O...

Page 23: ...OUT0 DVAL_OUT DVAL_OUT PSYNC_OUT PSYNC_OUT SPI_OUT5 SPI_OUT5 SPI_OUT4 SPI_OUT4 SPI_OUT2 SPI_OUT2 SPI_OUT3 SPI_OUT3 SPI_CLK SPI_CLK SPI_OUT6 SPI_OUT6 SPI_OUT7 SPI_OUT7 SPI_IN1 SPI_IN1 SPI_IN0 SPI_IN0 S...

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