IRF IRAUDAMP6 User Manual Download Page 21

 

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IRAUDAMP6 REV 1

.0

 

 

 

 

 

 

For  startup  sequencing,  +/-B  supplies  startup  at  different  intervals.  As  +/-B  supplies  reach  +5  V 
and -5 V respectively, the analog supplies (+/-5 V) start charging and, once +B reaches ~16 V, V

CC

 

charges. Once –B reaches -20 V, the UVP is released and CSD and CStart start charging. Once 
+/-5 V  is  established,  the  click-noise  reduction  circuit  is  activated  through  the  SP  MUTE  control 
signal.  As  CSD  reaches  two-thirds  V

DD

,  the  Class  D  stage  starts  oscillating.  Once  the  startup 

transient has passed, SP MUTE is released (CStart reaches Ref1). The Class D amplifier is now 
operational, but the preamp output remains muted until CStart reaches Ref2. At this point, normal 
operation begins. The entire process takes less than three seconds. 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Fig 14, Conceptual Shutdown Sequencing of Power Supplies and Audio Section Timing 

 
Shutdown sequencing is initiated once UVP is activated. As long as the supplies do not discharge 
too quickly, the shutdown sequence can be completed before the IRS20957 trips UVP. Once UVP 
is  activated,  CSD  and  CStart  are  discharged  at  different  rates.  In  this  case,  threshold  Ref2  is 
reached  first  and  the  preamp  audio  output  is  muted.  Once  CStart  reaches  threshold  Ref1,  the 
click-noise  reduction  circuit  is  activated  (SP  MUTE).  It  is  then  possible  to  shutdown  the  Class  D 
stage (CSD reaches two-thirds V

DD

). This process takes less than 200 ms. 

 
 

V

CC

 

-B 

+B 

+5 V 

-5 V 

CStart 

CSD 

UVP@-20 V 

CSD= 2/3V

DD

 

CStart Ref1 

CStart Ref2 

Audio MUTE 

SP MUTE 

CHx_O 

Class D shutdown 

Time 

Music shutdown 

Summary of Contents for IRAUDAMP6

Page 1: ...orge Cerezo and Liwei Zheng CAUTION International Rectifier suggests the following guidelines for safe operation and handling of IRAUDAMP6 Demo board Always wear safety glasses whenever operating Demo...

Page 2: ...S OF SELF OSCILLATING FREQUENCY 18 SWITCHES AND INDICATORS 18 STARTUP AND SHUTDOWN 18 CLICK AND POP NOISE REDUCTION 19 STARTUP AND SHUTDOWN SEQUENCING 20 SELECTABLE DEAD TIME 23 LEVEL SHIFTERS 23 PROT...

Page 3: ...ut Power 250W x 2 channels 8 load Residual Noise 90 V IHF A weighted AES 17 filter Distortion 0 005 THD N 125W 8 Efficiency 96 250W 8 single channel driven Class D stage Multiple Protection Features O...

Page 4: ...mic Range 117dB 113dB A weighted AES 17 filter Single channel operation Residual Noise 22Hz 20kHzAES17 70 V 110 V Self oscillating 400kHz Damping Factor 2000 906 1kHz relative to 8 load Channel Separa...

Page 5: ...ection Setup Fig 1 Typical Test Setup Volume J7 J9 J1 J5 J3 R100 S1 S2 CH1 Output CH2 Output CH1 Input CH2 Input G Protection Normal S3 73 5V 8A DC supply 8 4 Ohm 8 4 Ohm 73 5V 8A DC supply J6 Audio S...

Page 6: ...counter clockwise minimum volume 7 Connect the dual power supply to J3 as shown on Fig 1 Power up 8 Turn ON the dual power supply The B supplies must be applied and removed at the same time 9 Red LED...

Page 7: ...ision Ap 21 Use an unbalanced floating signal from the generator outputs 22 Use balanced inputs taken across output terminals J1 and J5 23 Connect Ap frame ground to GND at terminal J7 J9 24 Select th...

Page 8: ...www irf com Page 8 of 46 IRAUDAMP6 REV 1 0 8 ohm load 4 ohm load Fig 3 IRAUDAMP6 Frequency response...

Page 9: ...Comment 1 1 Red Solid 2 Anlr THD NRatio Left 125WL 1 2 Blue Solid 2 Anlr THD NRatio Left 125WR 2 1 Magenta Solid 2 Anlr THD NRatio Left 25WL 2 2 Green Solid 1 Anlr THD NRatio Left 25WR 0 0001 100 0 0...

Page 10: ...Left 100 0 80 60 40 20 d B V 10 20k 20 50 100 200 500 1k 2k 5k 10k Hz Fig 5 1V output Frequency Spectrum Color Sweep Trace Line Style Thick Data Axis Comment 1 1 Red Solid 1 Fft Ch 1 Ampl Left 1 2 Bl...

Page 11: ...www irf com Page 11 of 46 IRAUDAMP6 REV 1 0 Fig 7 Channel separation vs frequency...

Page 12: ...to the carrier signal based modulation is that all the error in the audible frequency range is shifted to the inaudible upper frequency range by nature of its operation Also sigma delta modulation all...

Page 13: ...ted by demodulating the amplified PWM This is done by means of the LC low pass filter LPF formed by L4 and C34 which filters out the Class D switching carrier signal Power Supplies The IRAUDAMP6 has a...

Page 14: ...rgy will cause a larger voltage increase The IRAUDAMP6 has protection features that will shutdown the switching operation if the bus voltage becomes too high 82 V or too low 36 V One of the easiest co...

Page 15: ...ght loading impedance Fig 10 but is not thermally rated to handle continuous supersonic frequencies These supersonic input frequencies therefore should be avoided Separate mono RCA connectors provide...

Page 16: ...g to mute the system with an overall gain of less than 60 dB For best performance in testing the internal volume control should be set to 1 Vrms input will result in rated output power 250 W into 8 Ef...

Page 17: ...p itself will add distortion and noise to the input signal resulting in a gain through the Class D output stage and appearing at the output Even a few micro volts of noise can add significantly to the...

Page 18: ...o fault condition is present There are three switches on the reference design Switch S1 is an oscillator selector This three position switch is selectable for internal self oscillator middle position...

Page 19: ...the following characteristics 1 An impedance significantly lower than that of the speaker being shunted In this case the shunt impedance is 100 m compared to the normal 8 speaker impedance 2 When dea...

Page 20: ...ischarging of the voltage of CSD C11 on daughter board for CH1 of the IRS20957 is all that is required for complete sequencing The conceptual startup and shutdown timing diagrams are show in Figure 13...

Page 21: ...eaches Ref2 At this point normal operation begins The entire process takes less than three seconds Fig 14 Conceptual Shutdown Sequencing of Power Supplies and Audio Section Timing Shutdown sequencing...

Page 22: ...trip in a similar manner as described above Once the fault is cleared the system will reset similar sequence as startup Fig 15 Conceptual Click Noise Reduction Sequencing at Trip and Reset CStart CSD...

Page 23: ...t bias current of the DT pin a bias current of greater than 0 5 mA is suggested for the external resistor divider circuit Suggested values of resistance that are used to set a dead time are given belo...

Page 24: ...20957 Fig 18 Functional Block Diagram of Protection Circuit Implementation The external shutdown circuit will disable the output by pulling down CSD pins If the fault condition persists the protection...

Page 25: ...ectFET from an overload condition from positive load current by measuring drain to source voltage across RDS ON during its on state OCP shuts down the switching operation if the drain to source voltag...

Page 26: ...mful excessive supply voltages such as due to bus pumping at very low frequency continuous output in stereo mode Under Voltage Protection UVP UVP is provided externally to the IRS20957 UVP prevents un...

Page 27: ...on OTP A separate PTC resistor is placed in close proximity to the high side IRF6785 DirectFET MOSFET for each of the amplifier channels If the resistor temperature rises above 90 C the OTP is activat...

Page 28: ...with a thermal interface material TIM The pressure between DirectFET and TIM is controlled by depth of Heat Spreader s groove Choose TIM which is recommended by IR Refer to AN 1035 for more details TI...

Page 29: ...eet According to the stress requirement find strain range for the TIM Then calculate heat spreader groove depth as below Groove Depth DirectFET s Height TIM s Thickness strain DirectFET s height shoul...

Page 30: ...Pin height PCB thickness heatsink height substructure height thermal pad thickness 70 8 5 1 6 2 54 1 421 2 939mm expected length Spring length change Free length expected length 6 4 2 939 3 461mm Spr...

Page 31: ...resume the PWM If the short circuit persists the IRS20957 repeats try and fail sequences until the short circuit is removed Short Circuit in Positive and Negative Load Current Fig 23 Positive and Nega...

Page 32: ...www irf com Page 32 of 46 IRAUDAMP6 REV 1 0 Schematic...

Page 33: ...www irf com Page 33 of 46 IRAUDAMP6 REV 1 0...

Page 34: ...www irf com Page 34 of 46 IRAUDAMP6 REV 1 0...

Page 35: ...www irf com Page 35 of 46 IRAUDAMP6 REV 1 0...

Page 36: ...www irf com Page 36 of 46 IRAUDAMP6 REV 1 0 Fig 22 IRAUDAMP6 Schematic...

Page 37: ...3UF 2000VDC POLY FILM AXL 2 Digikey 14 PCE3101CT ND C35 C64 C65 C69 C79 CAP 10UF 16V ELECT FC SMD 5 Digikey 15 495 1311 ND C36 C53 CAP 10UF 400V METAL POLYPRO 2 Digikey 16 PCC2009CT ND C38 C42 C56 C60...

Page 38: ...8 FZT855CT ND Q1 Q3 TRANS NPN 150V 4000MA SOT 223 2 Digikey 49 MMBTA92DICT ND Q2 TRANSISTOR PNP 300V SOT 23 1 Digikey 50 MMBT5401DICT ND Q7 Q10 Q13 TRANS 150V 350MW PNP SMD SOT 23 3 Digikey 51 MMBT555...

Page 39: ...11 Digikey 80 P68KACT ND R85 R97 RES 68K OHM 1 8W 5 0805 SMD 2 Digikey 81 P4 7KACT ND R89 RES 4 7K OHM 1 8W 5 0805 SMD 1 Digikey 82 P100ACT ND R98 R114 R131 RES 100 OHM 1 8W 5 0805 SMD 3 Digikey 83 3...

Page 40: ...3 1 Digikey 116 BZT52C5V6 FDICT ND Z10 Z12 DIODE ZENER 5 6V 500MW SOD123 2 Digikey Table 2 IRAUDAMP6 Daughter board s Materials No P N Designator Description Quantity Vendor 1 445 2276 1 ND C1 C2 C3 C...

Page 41: ...T ND R24 R25 RESISTOR 4 7 OHM 1 8W 5 0805 2 Digikey 27 P10ACT ND R26 R27 R36 R37 R38 R39 RES 10 OHM 1 8W 5 0805 SMD 6 Digikey 28 P33KACT ND R28 R29 RES 33K OHM 1 8W 5 0805 SMD 2 Digikey 29 RHM2 2KARCT...

Page 42: ...teria as defined for class II PCB S standards Gerber Files Apertures Description All Gerber files stored in the attached CD ROM were generated from Protel Altium Designer Altium Designer 6 Each file n...

Page 43: ...www irf com Page 43 of 46 IRAUDAMP6 REV 1 0 Fig 25 IRAUDAMP6 Mother board PCB Top Overlay Top View...

Page 44: ...www irf com Page 44 of 46 IRAUDAMP6 REV 1 0 Fig 26 IRAUDAMP6 Mother board PCB Bottom Layer Top View...

Page 45: ...www irf com Page 45 of 46 IRAUDAMP6 REV 1 0 Fig 27 IRAUDAMP6 Daughter board PCB Top Overlay Top View Fig 28 IRAUDAMP6 Daughter board PCB Bottom Layer Top View...

Page 46: ...0 Revision changes descriptions Revision Changes description Date Rev 1 0 Released May 30 2010 WORLD HEADQUARTERS 233 Kansas St El Segundo California 90245 Tel 310 252 7105 Data and specifications su...

Page 47: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information International Rectifier IRAUDAMP6...

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