Intersil ZL2005P, User Manual

Page: 2 / 22

ZL2005PEV4
2 ZL2005PEV4DSr1.0
Functional Description
The ZL2005PEV4 provides the circuit required
to demonstrate the features of the ZL2005P in a
10Amp configuration. The ZL2005PEV4 has a
functionally-optimized layout that allows highly-
efficient operation to its maximum output current
(See board picture in Figure 2). The input power
connection is provided through banana jack
terminals. Stand-alone operation of the ZL2005P
is achieved by factory installed pin-strap settings
and pre-configuration via PMBus commands.
PMBus protocol communication is performed
via a SMBus interface using an external USB to
SMBus adaptor. PMBus commands can be used
to modify the settings of the evaluation platform.
Figure 3 shows the ZL2005P circuit schematic.
The circuit consists of the ZL2005P power
conversion and management IC with its minimal
component count.
The input voltage connection is made at J1 which
is labeled VIN+/-. J2 is the output connector for
the output voltage, VOUT+/-. The VIN+/- and
VOUT+/- connections are rated to 10 A.
Figure 4 shows the ZL2005PEV4 interface
schematic. It contains various circuits that
interface to the ZL2005P’s circuit. The hardware
enable function is controlled by a toggle switch
(SW1) on the ZL2005PEV4 board. External
temperature is monitored from a 2N3904
transistor (Q3) connected to the XTEMP pin.
This external temperature is read with the
READ_TEMPERATURE_2 PMBus command.
The power good status is indicated by the PG
LED at D11. The PG LED indicates the correct
state of the power good signal when power is
applied to the ZL2005PEV4 board. The right
angle headers at opposite ends of the board (J10
and J11) are available to daisy chain multiple
boards. The SMBus and Enable signals are
passed between these connectors. All header pins
and switch positions are labeled on the
ZL2005PEV4 board’s silkscreen as shown in
Figure 5.
The ZL2005P SMBus address is set by the
jumper applied to J12. The SA1 pin is strapped
by an 11k resistor to ground. The J12 jumper
applies a different resistor to the SA0 pin to
achieve the indicated SMBus address settings.
Note that power must be cycled to set a new
address.
Refer to Figures 5 through 10 for component
placement and board layout. The board layout
has been optimized for two-sided component
area and thermal performance. For ZL2005P
circuit layout design considerations refer to
Zilker Labs Application Note AN10 (Reference
1 on page 21).