Intersil SL71010BM50EV1Z, User Manual

Page: 6 / 12

UG136 Rev.0.00 Page 6 of 12
Oct 24, 2017
ISL71010BM50EV1Z 3. PCB Layout Guidelines
3. PCB Layout Guidelines
3.1 ISL71010BM50EV1Z Evaluation Board
3.2 ISL71010BM50EV1Z Evaluation Board Schematic
Figure 3. ISL71010BM50EV1Z Evaluation Board
Figure 4. ISL71010BM50EV1Z Evaluation Board Schematic
GND
RC
GND
LOAD
VIN VOUT
7
10µF
C
2
0.1µF
R
2
DNP
TP3
0.1µF
SOIC8
1000pF
U1
2
3
4
6
TP1
C
1
C
3
C
5
P1
P2
5
1
TP4
2.21kΩ
2
R
1
J1
C
4
10µF
8
1
TP2
5
6
7
8
3
4
1
2