Application Note 1935
2
AN1935.0
May 16, 2014
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ISL85003ADEMO1Z Schematic
ISL85003ADEMO1Z Board Layout
FIGURE 2. SILK SCREEN TOP
FIGURE 3. SILK SCREEN BOTTOM
DRAWN BY:
DATE:
ENGINEER:
DA
2/27/2014
TU BUI
TU BUI
GND
GND
0.1UF
BOOT
EN
EN
PG
PG
SS
SS
UNNAMED_1_POWERIND_I179_A
UNNAMED_1_SMCAP_I185_A
UNNAMED_1_SMCAP_I186_A
UNNAMED_1_SMCAP_I193_A
VCC
VC
C
VCC
VCC
VCC
VIN
VIN
VO
VO
VO
VO
A
A
A
A
A
C1
10UF
C7
DNP
22UF
C5
P9
200K
R14
1UF
C9
OPEN
C10
P7
R3
DNP
D2
1
2
3
R6
200K
P5
R11
0
C6
22UF
4.7PF
C4
P4
200K
R7
C2
10UF
301K
R1
ISL85003AFRZ
U1
1
SS
2
PG
3
EN/SS
4
FB
5
COMP
6
AGND
7
PHASE
8
PHASE
9
VIN
10
VIN
11
VDD
12
BOOT
13
EP
R2
57.6K
C3
C11
22UF
C8
DNP
4.7UH
L1
NOTE: If the IC is used in an application where the input test leads have large parasitic
inductance, the input electrolytic capacitor C
10
may be added to prevent transient
voltages on the input pin.
