User Guide 009
2
UG009.0
October 30, 2014
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What’s Inside
The evaluation kit contains the following:
• The ISL80113EVAL1Z with the appropriate parts installed
•
ISL80111, ISL80112, ISL80113
Datasheet
Test Steps
1. Select the desired output voltage by shorting one of the
jumpers from JP2 through JP5.
2. Connect both the BIAS and VIN supplies and the load. Enable
the IC using jumper JP6 (bottom position) or via a signal on
the center post, observe the output.
3. The shipped configuration is enabled and V
OUT
= 3.3V.
4. Scope shots taken from ISL8011xEVAL1Z boards.
Functional Description
The ISL8011xEVAL1Z provides a simple platform to evaluate
performance of the ISL8011x family of split supply LDOs.
Jumpers are provided to easily set popular output voltages.
The ISL80111, ISL80112 and ISL80113 are single-output LDOs
specified for 1A, 2A, 3A of output current and are optimized for
less than 2.5V and less output voltage conversions. The
ISL8011X supports V
IN
voltages down to 1V, provided a standard
legacy 2.9V or 5.5V is applied on the V
BIAS
pin. The output
voltage is adjustable from 0.8V to 3.3V.
An enable input, having a threshold <1V, allows the part to be
placed into a low quiescent current shutdown mode. A submicron
CMOS process is utilized for this product family to deliver
best-in-class analog performance and overall value for
applications in need of input voltage conversions to typically
below 2.5V. It also has the superior load transient regulation
unique to a NMOS power stage.
These LDOs consume significantly lower quiescent current as a
function of load compared to bipolar LDOs. This lower
consumption translates into higher efficiency and the ability to
consider packages with smaller footprints. The quiescent current
has been modestly compromised in design to enable leading
class fast load transient response and load regulation.
PCB Layout Guidelines
The following is an example of how to use vias to remove heat
from the IC.
Filling the thermal pad area with vias is recommended. A typical
via array is to fill the thermal pad footprint with vias spaced such
that they are center on center 3x the radius apart from each
other. Keep the vias small but not so small that their inside
diameter prevents solder from wicking through the holes during
reflow.
Connect all vias to the round plane. For efficient heat transfer, it
is important that the vias have low thermal resistance. Do not
use “thermal relief” patterns to connect the vias. It is important
to have a complete connection of the plated through-hole to each
plane.
FIGURE 3. PCB VIA PATTERN
