X0116715 Rev.1.0
Page 4
Jan.12.21
ISL73033SLHEV1Z User Manual
2. ISL73033SLHEV1Z PCB Guidelines
The ISL73033SLH BGA package ball assignment is placed to allow for a simplified layout and optimizing
performance. The following are the layout guidelines for external component placement and Printed Circuit Board
(PCB) routing.
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Place a 4.7µF or larger X7R rated ceramic capacitor near the VDD and VSS balls.
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Place a 4.7µF or larger X7R rated ceramic capacitor near the VDRV and SOURCE balls.
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If using a non-inverting configuration, the INB ball is co-located next to the VSS balls for connecting INB to
VSS. If using an inverting configuration, the IN ball is co-located next to the VDD ball for connecting IN to VDD.
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For the 100V GaN FET, connect the DRAIN close to the rectifier path to minimize parasitic inductance that may
cause ringing or overshoot during switching and potentially exceed the drain-to-source voltage of the GaN FET.
The DRAIN and SOURCE balls are the thermal dissipation path. Allow adequate areas of PCB copper to these
balls on the top layer to carry away heat. Renesas also recommends using a conductively filled via underneath the
balls to additional PCB layers to help carry heat away from the package.
2.1
Evaluation Board
Figure 2. ISL73033SLHEV1Z Evaluation Board (Top)
Figure 3. ISL73033SLHEV1Z Evaluation Board (Bottom)
