UG124 Rev.0.00
Page 5 of 9
Jul 24, 2017
ISL70321SEHDEMO1Z
3. Application Considerations
Figure 4. Sequencing On 3 POLs, RTDLY = 2ms
Figure 5. Sequencing Off 3 POLs, RTDLY = 2ms
Figure 6. VM Low to KILL, UP, and EN1
Figure 7. Auto Fault Clear and Reset Waveform
UP/INIT
POL1 VOUT
POL2 VOUT
POL3 VOUT
2ms/DIV
UP/INIT
POL1 VOUT
POL2 VOUT
POL3 VOUT
5ms/DIV
VM
KILL
EN1
UP
DONE
EN1
KILL
UP
Summary of Contents for ISL70321SEHDEMO1Z
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