4
The ISL6539 is capable of starting into a prebiased output
rail. Figure 4 shows the ISL6539 soft-starting both the V
DDQ
and V
TT
rails from POR with a prebias on the V
DDQ
rail.
Output Ripple
Figure 5 shows the ripple on both the V
DDQ
and V
TT
rails
with a 90° phase shift implemented between the two
regulators.
Figure 6 shows the ripple on both the V
DDQ
and V
TT
rails
with a no phase shift implemented between the two
regulators.
Transient Performance
Figure 7 shows both the V
DDQ
and V
TT
rails while the V
DDQ
rail is under transient loading.
FIGURE 4. START-UP INTO PREBIASED OUTPUT
FIGURE 5. OUTUPT RIPPLE - 90° PHASE SHIFT
Timebase: 500µs/DIV
V
DDQ
500mV/DIV
V
IN
1V/DIV
V
TT
500mV/DIV
Timebase: 2µs/DIV
V
DDQ (AC Coupled)
50mV/DIV
V
PHASE1
5V/DIV
V
PHASE2
5V/DIV
V
TT (AC Coupled)
50mV/DIV
FIGURE 6. OUTUPT RIPPLE - NO PHASE SHIFT
FIGURE 7. TRANSIENT LOAD ON V
DDQ
V
DDQ (AC Coupled)
50mV/DIV
V
PHASE1
5V/DIV
V
PHASE2
5V/DIV
V
TT (AC Coupled)
50mV/DIV
Timebase: 2µs/DIV
V
DDQ (AC Coupled)
100mV/DIV
V
TT (AC Coupled)
100mV/DIV
I
VDDQ
2A/DIV
Timebase: 100µs/DIV
Application Note 1278