3
Transient Performance
Figures 6 and 7 show the response of the output when
subjected to sourcing and sinking transient loading,
respectively.
Lossless Output Voltage Droop
Droop is an intentional sag in the output voltage that is
proportional to the output current. Although not necessary
for proper circuit operation, utilizing droop allows the
dynamic regulation to be improved by taking advantage of
static regulation requirements and expanding the available
headroom for transient edge output excursions. In practical
applications that are compared to a non-droop
implementation, the droop implementation requires fewer
output capacitors or better regulation with the same type and
number of output capacitors.
By moving the regulation point ahead of the output inductor
(at the PHASE node), droop becomes equal to the average
voltage drop across the output inductor’s DC resistance as
well as any distributed resistance. The droop circuitry is
simply an RC low pass filter placed across the output
inductor. This filter must have the same time constant that
the output inductor and it’s corresponding DCR have. The
design must be careful to include any parasitic impedances
of the PC board if the DCR of the inductor is very low.
The ISL6526/27 evaluation board does not have any
component footprints that would allow an implementation of
droop. This section is included in this application note as a
guideline in the event that droop is necessary in a design
utilizing the ISL6526 or ISL6527. Figure 8 shows a
schematic of the power stage and Type III compensation
network of an ISL6526/27 regulator with droop. The droop
circuitry is represented by resistor R
D
and capacitor C
D
. The
output of this low pass filter is fed directly into the feedback
compensation network of the regulator. To insure symmetric
output voltage excursions about the nominal voltage in
response to load transients, the output voltage should be
programmed to be above the nominal level by half the
calculated droop.
FIGURE 5. OUTPUT RIPPLE VOLTAGE
5
µ
s/DIV
V
OUT
at 300kHz
10mV/DIV
V
OUT
at 600kHz
10mV/DIV
FIGURE 6. SOURCING TRANSIENT
200
µ
s/DIV
Load Current
2A/DIV
V
OUT
at 300kHz
10mV/DIV
V
OUT
at 600kHz
10mV/DIV
FIGURE 7. SINKING TRANSIENT
200
µ
s/DIV
Load Current
2A/DIV
V
OUT
at 300kHz
10mV/DIV
V
OUT
at 600kHz
10mV/DIV
FIGURE 8. DROOP IMPLEMENTATION
+
R
FB
C
OUT
V
OUT
L
OUT
ISL6526
Q
U
FB
UGATE
COMP
LGATE
Q
L
VIN
OR
ISL6527
R
D
C
D
R
OS
DCR R
parasitic
AN1021
