2
AN1187.1
August 10, 2005
ISL59420/21EVAL1 Top View
TABLE 1. LOGIC TABLE
S
HIZ
ENABLE
OUT
0
0
0
IN0
1
0
0
IN1
-
-
1
Power-down
-
1
-
High Z
* C
b1
, C
b2
are approximate PCB trace capacitances.
FIGURE 2A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
* C
b1
is approximate PCB trace capacitance.
FIGURE 2B. TEST CIRCUIT FOR 50
Ω
OR 75
Ω
TERMINATIONS
* C
b1
is approximate PCB trace capacitance.
FIGURE 2C. BACK-TERMINATED TEST CIRCUIT FOR CABLE
APPLICATION
FIGURE 2D. R
F
TABLE FOR FIGURE 2 CIRCUITS
ISL59420, ISL59421
*C
b1
50
Ω
V
IN
500
Ω
R
L
~0.5pF
OR
75
Ω
*C
b2
~3pF
C
L
1.5pF
R
S
, 0
Ω
+
-
R
F
ISL59420, ISL59421
R
S
V
IN
475
Ω
TEST
~0.5pF
50
Ω
OR
75
Ω
50
Ω
OR
75
Ω
50
Ω
OR
75
Ω
R
L
EQUIPMENT
C
b1
+
-
R
F
ISL59420, ISL59421
R
S
C
b1
V
IN
50
Ω
OR 75
Ω
TEST
~0.5pF
50
Ω
OR
75
Ω
50
Ω
OR
75
Ω
EQUIPMENT
R
F
+
-
PART #
R
F
VALUE
ISL59420
200
Ω
ISL59421
357
Ω
Application Note 1187
