1
TM
AN9966
ISL5x61EVAL1 and EVAL2 User’s Manual
Description
The ISL5x61EVAL1 and EVAL2 evaluation boards provide a
quick and easy method for evaluating the
ISL5761/5861/5961 (10-, 12-, or 14-bit), 130/210MSPS high
speed DACs. EVAL1 is populated with an SOIC package and
EVAL2 is populated with a TSSOP package. The board is
configured so that the converter outputs differential current
into a transformer circuit to form an output voltage. The
amount of current out of the DAC is determined by an
external resistor and either an internal or external reference
voltage. The CMOS digital inputs have optional external
termination resistors. The evaluation board includes a ribbon
cable digital interface that is compatible with Intersil DUC
(Digital Up Converter) evaluation boards like the ISL5217.
Features
• 210MSPS 10-, 12- or 14-Bit CMOS DAC
• Transformer-Coupled or Single-Ended SMA Outputs
• Interface compatible to the ISL5217 Digital Up Converter
allows complete Baseband-to-IF Demonstration
Functional Block Diagram
Getting Started
See Figure 1. A summary of the equipment, external
supplies and signal sources needed to operate the board is
given below:
1. +3.3V supply for ISL5x61 DAC.
2. Pattern generator (pattern source).
3. Square wave, DC-biased clock source (usually part of the
pattern generator).
4. Spectrum analyzer or oscilloscope for viewing the output
of the converter.
Attach the evaluation board to the power supply(s). Connect
the bits from the data generator to the evaluation board
using the 2x20 pin connector (J1). Connect the clock source
to the evaluation board, either through the 2x20 pin
connector (J1) or via the provided SMA (J2).
Using a coaxial cable with the proper SMA connector, attach
the output of the converter, I
OUT
(J11), to the measurement
equipment that will be evaluating the converter’s
performance. Make sure that the jumpers are in their proper
placement (default placement should be J5 and J10
populated, all others not populated).
Set the clock signal and data levels to swing from 0-3V. Turn
the power supply on. Turn the pattern and clock on and
measure the result at the analog output SMA (J11).
Ordering Information
PART
NUMBER
TEMP.
RANGE
(
o
C)
PACKAGE
NUMBER
OF BITS
CLOCK
SPEED
ISL5761EVAL1
25
SOIC
10
210MHz
ISL5861EVAL1
25
SOIC
12
210MHz
ISL5961EVAL1
25
SOIC
14
210MHz
ISL5761EVAL2
25
TSSOP
10
210MHz
ISL5861EVAL2
25
TSSOP
12
210MHz
ISL5961EVAL2
25
TSSOP
14
210MHz
10-14 BITS
CLOCK
XFMR
IOUTA
IOUTB
IOUT
T1
SMA
SMA
SMA
CLK
SMA
DAC
AGND PLANE
DVDD PLANE
AVDD PLANE
DGND PLANE
2x20
PI
N
HEADER
Application Note
September 2001
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Copyright © Intersil Americas Inc. 2001, All Rights Reserved
