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51
BIOS
SERR#
Set this option to Enabled to enable the SERR# signal on the bus. The
settings are Enabled or Disabled. The Optimal and Fail-safe default
settings are Disabled.
PERR#
Set this option to Enabled to enable the PERR# signal on the bus. The
settings are Enabled or Disabled. The Optimal and Fail-safe default
settings are Disabled.
WSC# Handshake
Set this option to Enabled to enable handshaking for the WSC# signal.
Handshaking is a form of encryption; see the Glossary for more infor-
mation. The settings are Enabled or Disabled. The Optimal and Fail-
safe default settings are Enabled.
USWC Write Post
This option sets the status of USWC posted writes to I/O. USWC is a
type of memory that is used by VGA devices. The settings are:
The Optimal and Fail-safe default settings are Enabled.
BX Master Latency Timer (Clks)
This option specifies the master latency timer (in PCI clocks) for
devices in the computer. The settings are Disabled, 32, 64, 96, 128,
160, 192, or 224. The Optimal and Fail-safe default settings are 64.
Multi-Trans Timer (Clks)
This option specifies the multi-trans latency timings (in PCI clocks) for
devices in the computer. The settings are Disabled, 32, 64, 96, 128,
160, 192, or 224. The Optimal and Fail-safe default settings are 64.
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