Intel® Xeon® Processor 5600 Series
25
Specification Update, March 2010
BD25.
Intel® QuickPath Memory Controller May Hang Due to Uncorrectable
ECC Errors Occurring on Both Channels in Mirror Channel Mode
Problem:
If an uncorrectable ECC error or parity error occurs on the mirrored channel before an
uncorrectable ECC error or parity error on the other channel can be resolved, the Intel
QuickPath Memory Controller will hang without an uncorrectable ECC or parity error
being logged.
Implication:
The processor may hang and not report the error when uncorrectable ECC or parity
errors occur in close proximity on both channels in a mirrored channel pair. No
uncorrectable ECC or parity error will be logged in the machine check banks.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD26.
Simultaneous Correctable ECC Errors on Different Memory Channels
With Patrol Scrubbing Enabled May Result in Incorrect Information
Being Logged
Problem:
When a correctable patrol scrub ECC error occurs simultaneously with a correctable
system read ECC error on different memory channels, IA32_MCi_STATUS and
IA32_MCi_MISC should log the system read error. Due to this erratum IA32_MCi_MISC
may incorrectly contain the patrol scrub error information and the IA32_MCi_ADDR
may not be correct.
Implication:
IA32_MCi_MISC and IA32_MCi_STATUS information may be inconsistent.
IA32_MCi_ADDR may be incorrect.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD27.
The Memory Controller tTHROT_OPREF Timings May be Violated
During Self Refresh Entry
Problem:
During self refresh entry, the memory controller may issue more refreshes than
permitted by tTHROT_OPREF (bits 29:19 in MC_CHANNEL_{0,1,2}_REFRESH_TIMING
CSR).
Implication:
The intention of tTHROT_OPREF is to limit current. Since current supply conditions near
self refresh entry are not critical, there is no measurable impact due to this erratum.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD28.
Synchronous Reset of IA32_APERF/IA32_MPERF Counters on
Overflow Does Not Work
Problem:
When either the IA32_MPERF or IA32_APERF MSR (E7H, E8H) increments to its
maximum value of 0xFFFF_FFFF_FFFF_FFFF, both MSRs are supposed to synchronously
reset to 0x0 on the next clock. This synchronous reset does not work. Instead, both
MSRs increment and overflow independently.
Implication:
Software can not rely on synchronous reset of the IA32_APERF/IA32_MPERF registers.
Workaround:
None identified.
Status:
