Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU Documentation Update Download Page 49 | Manualshive

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Errata

Specification Update

49

AZ66.

XRSTOR Instruction May Cause Extra Memory Reads

Problem:

An XRSTOR instruction will cause non-speculative accesses to XSAVE memory area
locations containing the FCW/FSW and FOP/FTW Floating Point registers even though the
64-bit restore mask specified in the EDX:EAX register pair does not indicate to restore
the x87 FPU state.

Implication:

Page faults, data breakpoint triggers, etc. may occur due to the unexpected
nonspeculative accesses to these memory locations.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the Summary Tables of Changes.

AZ67.

LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode

Problem:

An exception/interrupt event should be transparent to the LBR (Last Branch Record), BTS
(Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However, during a
specific boundary condition where the exception/interrupt occurs right after the
execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF) in 64-
bit mode, the LBR return registers will save a wrong return address with bits 63 to 48
incorrectly sign extended to all 1s. Subsequent BTS and BTM operations which report
the LBR will also be incorrect.

Implication:

LBR, BTS and BTM may report incorrect information in the event of an
exception/interrupt.

Workaround:

None identified.

Status:

For the steppings affected, see the Summary Tables of Changes.

AZ68.

When Intel® Deep Power-Down State is Being Used, IA32_FIXED_CTR2
May Return Incorrect Cycle Counts

Problem:

When the processor is operating at an N/2 core to front side bus ratio, after exiting an
Intel Deep Power-Down state, the internal increment value for IA32_FIXED_CTR2 MSR
(Fixed Function Performance Counter 2, 30BH) will not take into account the half ratio
setting.

Implication:

Due to this erratum, IA32_FIXED_CTR2 MSR will not return reliable counts after
returning from an Intel Deep Power-Down state.

Workaround:

It is possible for the

BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the Summary Tables of Changes.

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Summary of Contents for T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU

Page 1: ... Intel Core 2 Quad Mobile Processor Intel Core 2 Extreme Mobile Processor Intel Core 2 Duo Mobile Processor Intel Core 2 Solo Mobile Processor and Intel Celeron Processor on 45 nm Process Specification Update December 2011 Document Number 320121 008 ...

Page 2: ...e is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Intel processor numbers are not a measure of performance Processor numbers differentiate features w...

Page 3: ...Specification Update 3 Contents Preface 5 Identification Information 7 Summary Tables of Changes 13 Errata 21 Specification Changes 53 Specification Clarifications 54 Documentation Changes 56 ...

Page 4: ... AZ65 AZ66 August 2008 320121 003 1 0 Added Erratum AZ66 74 October 2008 320121 004 1 0 Added Erratum AZ75 Added Specification Clarification AZ2 November 2008 320121 005 1 0 Table 1 added new skus and updated E and R step information Errata table added R step information March 2009 320121 006 1 0 S SPEC updated for new E and R step in Table 1 April 2009 320121 007 1 0 Added Erratum AZ76 December 2...

Page 5: ...or Intel Core 2 Quad Mobile Processor Intel Core 2 Extreme Mobile Processor Intel Core 2 Duo Mobile Processor Intel Core 2 Solo Mobile Processor and Intel Celeron Processor on 45 nm Process for Platforms based on Mobile Intel 4 Series Express Chipset family Datasheet 320120 Intel Core 2 Extreme Quad Core Processor Processors and Intel Core 2 Quad Processor on 45 nm Process for Platforms based on M...

Page 6: ...e etc as described in the processor identification information table Read all notes associated with each S Spec number Specification Changes are modifications to the current published specifications These changes will be incorporated in any new release of the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a com...

Page 7: ...e Intel386 Intel486 Pentium Pentium Pro Pentium 4 or Intel Core processor family 2 The Extended Model bits 19 16 in conjunction with the Model Number specified in bits 7 4 are used to identify the model of the processor within the processor s family 3 The Processor Type specified in bits 13 12 indicates whether the processor is an original OEM processor an OverDrive processor or a dual processor c...

Page 8: ...n The processor stepping can be identified by the following component markings Figure 1 Processor S Spec Top side Markings Example MARK EXAMPLE Group 1 Line 1 Unit Identifier Processor Group 1 Line 2 FPO SSPEC Group 2 Line 1 Frequency L2 Cache FSB Speed Group 2 Line 2 INTEL m 07 ...

Page 9: ... 0 8 800 2 3 35 3 2 3 4 SLAZD T8100 m FCPGA M 0 000010676h 2 1 1 2 0 8 800 2 3 35 3 2 3 4 7 SLAYZ T8100 m FCPGA M 0 000010676h 2 1 1 2 0 8 800 2 3 35 3 2 3 4 7 SLAZC T8300 m FCPGA M 0 000010676h 2 4 1 2 0 8 800 2 6 35 3 2 3 4 7 SLAZB T9300 m FCPGA C 0 000010676h 2 5 1 2 0 8 800 2 7 35 6 2 3 4 7 SLAYY T9300 m FCPGA C 0 000010676h 2 5 1 2 0 8 800 2 7 35 6 2 3 4 7 SLAZA T9500 m FCPGA C 0 000010676h 2...

Page 10: ...17 6 18 SLB5J QX9300 m FCPGA E 0 00001067Ah 2 53 1 6 n a 1066 2 8 45 12 14 15 16 SLB5G Q9100 m FCPGA E 0 00001067Ah 2 26 1 6 n a 1066 2 53 45 12 14 15 16 SLB64 SP9400 m FCBGA C 0 000010676h 2 40 1 6 0 8 1066 2 53 25 6 17 6 18 SLB63 SP9300 m FCBGA C 0 000010676h 2 26 1 6 0 8 1066 2 40 25 6 17 6 18 SLB66 SL9400 m FCBGA C 0 000010676h 1 86 1 6 0 8 1066 2 13 17 6 19 6 20 SLB65 SL9300 m FCBGA C 0 00001...

Page 11: ...1 2 0 8 800 N A 5 5 3 34 13 SLGEV 743 m FCBGA R 0 00001067Ah 1 3 n a n a 800 N A 10 1 35 13 SLGQQ SU3500 m FCBGA R 0 00001067Ah 1 4 1 2 0 8 800 N A 5 5 3 34 13 NOTES 1 Does not support Intel Dynamic Acceleration Technology 2 Vcc core VID 1 000 1 250 0 850 1 250 V HFM LFM 0 750 0 925 V S LFM 3 Vcc core VID 0 650 0 859 0 600 0 850 0 350 0 700 V C4 DC4 C6 4 Vcc core VID 1 000 1 300 IDAT 5 Vcc core VI...

Page 12: ...5 0 95 V S LFM 30 Vcc core VID 0 90 1 25 IDAT 31 Vcc core VID 0 775 1 100 0 80 0 975 V HFM LFM 0 750 0 925 V S LFM 32 Vcc core VID 0 65 0 80 0 60 0 80 0 35 0 60 V C4 DC4 C6 33 Vcc core VID 0 80 1 1625 IDAT 34 Vcc core VID 0 80 1 25 VID 35 Vcc core VID 0 775 1 10 VID 36 Vcc core VID 0 900 1 2125 0 850 1 025 V HFM LFM 0 75 0 95 V S LFM 37 Vcc core VID 0 900 1 2125 0 850 1 025 V HFM LFM 0 75 0 95 V S...

Page 13: ...hanges as noted This table uses the following notations Codes Used in Summary Table Stepping X Erratum Specification Change or Clarification that applies to this stepping No mark or Blank Box This erratum is fixed in listed stepping or specification change does not apply to listed stepping Status Doc Document change or update that will be implemented PlanFix This erratum may be fixed in a future s...

Page 14: ...nd 2 MB L2 cache versions T Mobile Intel Pentium 4 processor M U 64 bit Intel Xeon processor MP with up to 8MB L3 Cache V Mobile Intel Celeron processor on 13 Micron Process in Micro FCPGA Package W Intel Celeron M processor X Intel Pentium M processor on 90 nm process with 2 MB L2 cache and Intel Processors A100 and A110 with 512 KB L2 cache Y Intel Pentium M processor Z Mobile Intel Pentium 4 pr...

Page 15: ...el Xeon processor 5200 series AZ Intel Core 2 Extreme Quad Core Mobile Processor Intel Core 2 Quad Mobile Processor Intel Core 2 Extreme Mobile Processor Intel Core 2 Duo Mobile Processor Intel Core 2 Solo Mobile Processor and Intel Celeron Processor on 45 nm Process AAA Quad Core Intel Xeon processor 3300 series AAB Dual Core Intel Xeon E3110 Processor AAC Intel Celeron dual core processor E1000 ...

Page 16: ... a MONITOR MWAIT Address Range May Prevent Triggering of the Monitoring Hardware AZ10 X X X X No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over Count AZ11 X X X X No Fix The Processor May Report a TS Instead of a GP Fault AZ12 X X X X No Fix Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check AZ13 X X X X No Fix A Write to an APIC Register Sometimes May Appear to Have Not ...

Page 17: ...ed Stores May not Trigger the Monitoring Hardware AZ30 X X X X No Fix Programming the Digital Thermal Sensor DTS Threshold May Cause Unexpected Thermal Interrupts AZ31 X X X X No Fix Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue AZ32 X X X X No Fix General Protection GP Fault May Not Be Signaled on Data Segment Limi...

Page 18: ...nexpected Processor Behavior AZ49 X X X X Plan Fix RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results AZ50 X X X X No Fix Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown AZ51 X X X X No Fix LER MSRs May Be Incorrectly Updated AZ52 X X X X Plan Fix Processor May Unexpectedly Assert False THERMTRIP After...

Page 19: ...8 X X No Fix When Intel Deep Power Down State is Being Used IA32_FIXED_CTR2 May Return Incorrect Cycle Counts AZ69 X X No Fix Enabling PECI via the PECI_CTL MSR Incorrectly Writes CPUID_FEATURE_MASK1 MSR AZ70 X X X X No Fix Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode AZ71 X X No Fix The XSAVE Instruction May Erroneously Set Reserved Bits in the...

Page 20: ...FICATION CLARIFICATIONS AZ1 Clarification of Translation Lookaside Buffers TLBS Invalidation AZ2 CPUID Instruction Will Return Brand String With a Missing Letter Number DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision ...

Page 21: ... entry for the store address must have its permissions tightened during the very small window of time between the DTLB eviction and execution of the store Examples of page permission tightening include from Present to Not Present or from Read Write to Read Only etc 3 Another processor without corresponding synchronization and TLB flush must cause the permission change Implication This scenario may...

Page 22: ...s Problem When data of Store to WT memory is used by two subsequent loads of one thread and another thread performs cacheable write to the same address the first load may get the data from external memory or L2 written by another core while the second load will get the data straight from the WT Store Implication Software that uses WB to WT memory aliasing may violate proper store ordering Workarou...

Page 23: ...Code PF Problem Code PF Page Fault exception is normally handled in lower priority order relative to both code DB Debug Exception and code Segment Limit Violation GP General Protection Fault Due to this erratum code PF may be handled incorrectly if all of the following conditions are met Implication A PDE Page Directory Entry is modified without invalidating the corresponding TLB Translation Look ...

Page 24: ...MX instructions including EMMS are executed immediately after the last FP instruction a FP to MMX technology transition may not be counted Implication The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active Intel has not observed this erratum with...

Page 25: ...ask State Segment may cause a TS invalid TSS exception instead of a GP fault general protection exception Implication Operation systems that access a busy TSS may get invalid TSS fault instead of a GP fault Intel has not observed this erratum with any commercially available software Workaround None identified Status For the steppings affected see the Summary Tables of Changes AZ12 Code Segment Lim...

Page 26: ...lly set i e by STI instruction Interrupts will remain pending and are not lost Implication In this example the processor may allow interrupts to be accepted but may delay their service Workaround This non synchronization can be avoided by issuing an APIC register read after the APIC register write This will force the store to the APIC register before any subsequent instructions are executed No com...

Page 27: ...will now always be 8 bytes as opposed to the original data size WP the data size of each write will now always be 8 bytes as opposed to the original data size and there may be a memory ordering violation WT there may be a memory ordering violation Workaround Software should avoid crossing page boundaries from WB or WC memory type to UC WP or WT memory type within a single REP MOVS or REP STOS inst...

Page 28: ...rom System Management Mode returns to execution flow that results in a Code Segment Limit or Canonical Fault the GP fault may be serviced before a higher priority Interrupt or Exception e g NMI Non Maskable Interrupt Debug break DB Machine Check MC etc Implication Operating systems may observe a GP fault being serviced before higher priority Interrupts and Exceptions Intel has not observed this er...

Page 29: ...d has a floating point exception pending If an MMX or SSE SSE2 SSE3 SSSE3 extensions SSE instruction that performs a memory load and has either CR0 EM 1 Emulation bit set or a floating point Top of Stack FP TOS not equal to 0 or a DNA exception pending Implication In normal code execution where the target of the load operation is to write back memory there is no impact from the load being prematur...

Page 30: ...may be a smaller than expected value in the INST_RETIRED performance monitoring counter The extent to which this value is smaller than expected is determined by the frequency of the above cases Workaround None identified Status For the steppings affected see the Summary Tables of Changes AZ23 Returning to Real Mode from SMM with EFLAGS VM Set May Result in Unpredictable System Behavior Problem Ret...

Page 31: ...LVT When an Interrupt Is Pending May Cause an Unexpected Interrupt Problem If a local interrupt is pending when the LVT entry is written an interrupt may be taken on the new interrupt vector even if the mask bit is set Implication An interrupt may immediately be generated with the new vector when a LVT entry is written even if the new LVT entry has the mask bit set If there is no Interrupt Service...

Page 32: ...ication 2 VERW ZF 0 indicates unsuccessful segment write verification 3 LAR ZF 0 indicates unsuccessful access rights load 4 LSL ZF 0 indicates unsuccessful segment limit load Implication The value of the LER MSR may be inaccurate if VERW VERR LSL LAR instructions are executed after the occurrence of an exception Workaround Software exception handlers that rely on the LER MSR value should read the...

Page 33: ...interrupt enable bit When programming DTS value the previous DTS threshold may be crossed This will generate an unexpected thermal interrupt Implication Software may observe an unexpected thermal interrupt occur after reprogramming the thermal threshold Workaround In the ACPI OS implement a workaround by temporarily disabling the DTS threshold interrupt before updating the DTS threshold value Stat...

Page 34: ...in a processor shutdown If the MCE is called with a stack switch e g when the CPL Current Privilege Level was changed or when going through an interrupt task gate then the corrupted ESP will be saved on the new stack or in the TSS Task State Segment and will not be used Workaround Use an interrupt task gate for the machine check handler Status For the steppings affected see the Summary Tables of C...

Page 35: ...n systems using C states C2 Stop Grant State and higher the result could be a system hang Workaround BIOS must leave the xTPR update transactions disabled default Status For the steppings affected see the Summary Tables of Changes AZ37 Performance Monitoring Event IA32_FIXED_CTR2 May Not Function Properly When Max Ratio Is a Non Integer Core to Bus Ratio Problem Performance Counter IA32_FIXED_CTR2...

Page 36: ...o report a machine check exception MCE This would occur if one of the addresses is non cacheable and used in a code segment and the other is a cacheable address If the cacheable address finds its way into the instruction cache and the non cacheable address is fetched in the IFU the processor may invalidate the non cacheable address from the fetch unit Any micro architectural event that causes inst...

Page 37: ...hadow in the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B a VM exit occurs immediately after any VM entry performed with the use TPR shadow activate secondary controls and virtualize APIC accesses VM execution controls all set to 1 and with the value of the TPR shadow bits 7 4 in byte 80H of the virtual APIC page less than the TPR threshold VM execution control field Due ...

Page 38: ...Due to this erratum such VM exits always save zero into the RIP field of the guest state area of the virtual machine control structure VMCS instead of the value of RIP before the SIPI was received Implication In the absence of virtualization a SIPI received by a logical processor in the wait for SIPI state results in the logical processor starting execution from the vector sent in the SIPI regardl...

Page 39: ...uence May Cause the Processor to Hang Problem Under some rare conditions when multiple streaming load instructions MOVNTDQA are mixed with non streaming loads that split across cache lines the processor may hang Implication Under the scenario described above the processor may hang Intel has not observed this erratum with any commercially available software Workaround It is possible for the BIOS to...

Page 40: ...ion under rare scenarios the processor may hang Implication The cacheline split load operation may not be able to complete normally and the machine may hang and generate Machine Check Exception Intel has not observed this erratum with any commercially available software Workaround It is possible for the BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary...

Page 41: ...BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes AZ50 Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown Problem According to the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A Exception and Interrupt Reference if another exception occurs while attempting to call the double fault handl...

Page 42: ...m the ratio used at power on The issue is due to a thermal sensor circuit timing marginality event that causes the sensor to initiate a thermal shutdown Under these conditions upon RESET assertion some processors may assert a false THERMTRIP even though their temperature is below normal THERMTRIP activation temperature A warm reset is different from a cold power on reset in that PWRGOOD remains ac...

Page 43: ... a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes AZ54 IA32_MC1_STATUS MSR Bit 60 Does Not Reflect Machine Check Error Reporting Enable Correctly Problem IA32_MC1_STATUS MSR 405H bit 60 EN Error Enabled is supposed to indicate whether the enable bit in the IA32_MC1_CTL MSR 404H was set at the time of the last update to the IA32_MC1_STATUS MSR Due to...

Page 44: ...hitecture Software Developer s Manual the use of MOV SS POP SS in conjunction with MOV r e SP r e BP will avoid the failure since the MOV r e SP r e BP will not generate a floating point exception Developers of debug tools should be aware of the potential incorrect debug event signaling created by this erratum Status For the steppings affected see the Summary Tables of Changes AZ56 Code Segment Li...

Page 45: ...nd VMM software should follow the guidelines given in the section Handling VM Exits Due to Exceptions of Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide Status For the steppings affected see the Summary Tables of Changes AZ58 A VM Exit Occurring in IA 32e Mode May Not Produce a VMX Abort When Expected Problem If a VM exit occurs while the processor i...

Page 46: ...ly be observed with a software generated stack frame Workaround Software should not generate misaligned stack frames for use with IRET Status For the steppings affected see the Summary Tables of Changes AZ60 Thermal Interrupts are Dropped During and While Exiting Intel Deep Power Down State Problem Thermal interrupts are ignored while the processor is in Intel Deep Power Down State as well as duri...

Page 47: ...he VM entry MSR load area for the IA32_DEBUGCTL MSR 1D9H the value in the entry should set the FREEZE_WHILE_SMM_EN bit In addition the VMM should use VMWRITE to clear the FREEZE_WHILE_SMM_EN bit in the guest IA32_DEBUGCTL field before every VM entry It is necessary to do this before every VM entry because each VM exit will save that bit as 1 This workaround prevents the VM entry failure and sets t...

Page 48: ...ECX and or EDX values may be incorrect Implication When this erratum occurs the processor may report an incorrect brand string Workaround It is possible for the BIOS to contain a workaround for this erratum Workaround does NOT work for SLB5J and SLGAS processors Status For the steppings affected see the Summary Tables of Changes AZ65 Global Instruction TLB Entries May Not be Invalidated on a VM Ex...

Page 49: ...rrupt occurs right after the execution of an instruction at the lower canonical boundary 0x00007FFFFFFFFFFF in 64 bit mode the LBR return registers will save a wrong return address with bits 63 to 48 incorrectly sign extended to all 1s Subsequent BTS and BTM operations which report the LBR will also be incorrect Implication LBR BTS and BTM may report incorrect information in the event of an except...

Page 50: ...ction Enable bit 0 and the first far JMP the subsequent RSM Resume from System Management Mode may cause the lower two bits of CS segment register to be corrupted Implication The corruption of the bottom two bits of the CS segment register will have no impact unless software explicitly examines the CS segment register between enabling protected mode and the first far JMP Intel 64 and IA 32 Archite...

Page 51: ...undary without serialization Workaround It is possible for the BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes AZ74 The XRSTOR Instruction May Fail to Cause a General Protection Exception Problem The XFEATURE_ENABLED_MASK register XCR0 bits 63 9 are reserved and must be 0 consequently the XRSTOR instruction should cause a general pr...

Page 52: ...of conditions in 64 bit mode a register IP Relative instruction may be incorrect Implication A register IP relative instruction result may be incorrect and could cause software to read from or write to an incorrect memory location This may result in an unexpected page fault or unpredictable system behavior Workaround It is possible for the BIOS to contain a workaround for this erratum Status For t...

Page 53: ...Specification Changes Specification Update 53 Specification Changes There are no specification changes for this specification update revision ...

Page 54: ...ructure caches and TLB invalidation In rare instances improper TLB invalidation may result in unpredictable system behavior such as system hangs or incorrect data Developers of operating systems should take this documentation into account when designing TLB invalidation algorithms AZ2 CPUID Instruction Will Return Brand String With a Missing Letter The Specification Clarification listed in this se...

Page 55: ...how the correct and full processor number with the first letter S or letter X Table 1 Documentation Clarification Processor Number in Datasheet Processor Number in Brand String Displayed SP9400 P9400 SP9300 P9300 SL9400 L9400 SL9300 L9300 SU9400 U9400 SU9300 U9300 SU3300 U3300 QX9300 Q9300 ...

Page 56: ...Documentation Changes 56 Specification Update Documentation Changes There are no documentation changes for this specification update revision ...

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