Intel SSDSA1MH080G1 Product Manual Download Page 20

Intel

®

 X18-M/X25-M SATA SSD

Intel

®

 X18-M/X25-M SATA Solid State Drive

Product Manual

May 2009

20

Order Number: 319765-008US

Intel

®

 X18-M/X25-M SATA SSD

6.1.1.1

IDENTIFY DEVICE Data

The following table details the sector data returned after issuing an IDENTIFY DEVICE 

command.

Table 16.

Returned Sector Data

Word

F = Fixed

V = Variable

X = Both

Default Value

Description

0

 F

0040h

General configuration bit-significant information

1

X

3FFFh

Obsolete - Number of logical cylinders (16,383)

2

V

C837h

Specific configuration

3

X

0010h

Obsolete - Number of logical heads (16)

4-5

X

0h

Retired

6

X

003Fh

Obsolete - Number of logical sectors per logical track (63)

7-8

V

0h

Reserved for assignment by the CompactFlash Association

9

X

0h

Retired

10-19

F

Varies

Serial number (20 ASCII characters)

20-21

X

0h

Retired

22

X

0h

Obsolete

23-26

F

Varies

Firmware revision (8 ASCII characters)

27-46

F

Varies

Model number (Intel Solid State Drive)

47

F

8010h

7:0—Maximum number of sectors transferred per interrupt on MULTIPLE 

commands

48

F

0h

Reserved

49

F

2F00h

Capabilities

50

F

4000h Capabilities

51-52

X

0h

Obsolete

53

F

0007h

Words 88 and 70:64 Valid

54

X

3FFFh

Obsolete - Number of logical cylinders (16,383)

55

X

0010h

Obsolete - Number of logical heads (16)

56

X

003Fh

Obsolete - Number of logical sectors per logical track (63)

57-58

X

00FBFC10h

Obsolete

59

F

0101h

Number of sectors transferred per interrupt on MULTIPLE commands

60-61

F

0950F8B0h

(80 GB)

0FFFFFFFh

(160 GB)

Total number of user addressable sectors 

62

X

0h

Obsolete

63

F

0007h

Multi-word DMA modes supported/selected

64

F

0003h

PIO modes supported

65

F

0078h 

Minimum Multiword DMA transfer cycle time per word

66

F

0078h 

Manufacturer’s recommended Multiword DMA transfer cycle time

67

F

0078h

Minimum PIO transfer cycle time without flow control

68

F

0078h

Minimum PIO transfer cycle time with IORDY flow control

Summary of Contents for SSDSA1MH080G1

Page 1: ...6 compliant compatible with SATA 1 5 Gb s and 3 Gb s interface rates ATA ATAPI 7 Compliant SSD Enhanced SMART ATA feature set Native Command Queuing NCQ command set Certifications UL CE C Tick BSMI M...

Page 2: ...se for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Except as permitted by such license no part of this document...

Page 3: ...imum Useful Life 11 4 0 Mechanical Information 11 4 1 1 8 5 mm Intel X18 M SATA SSD 11 4 2 1 8 8 mm Intel X18 M SATA SSD 13 4 3 2 5 7 mm Intel X25 M SATA SSD 14 4 4 2 5 9 5 mm Intel X25 M SATA SSD 15...

Page 4: ...Intel X18 M X25 M SATA SSD Intel X18 M X25 M SATA Solid State Drive Product Manual May 2009 4 Order Number 319765 008US 9 0 Revision History 27...

Page 5: ...al seek time that can slow down the storage subsystem significantly the Intel X18 M X25 M SATA SSD enables fast read write access times and a significant I O and throughput performance improvement as...

Page 6: ...lash Memory Channel n NAND Flash Memory NAND Flash Memory NAND Flash Memory Table 1 Device Certifications Certification Description CE Compliant Indicates conformity with the essential health and safe...

Page 7: ...imate performance as measured by that configuration Any difference in system hardware or software design or configuration may affect actual performance MIC Certified Compliance with paragraph 1 of Art...

Page 8: ...r with queue depth set to 32 2 Write Cache enabled 3 Measurements are performed on 8 GB span 3 3 Electrical Characteristics 3 3 1 Supply Voltage 3 3 2 Power Consumption Note Active power is measured d...

Page 9: ...mounted securely with the input vibration applied to the drive mounting screws Stimulus may be applied in the X Y or Z axis The measured specification is in root mean sqaured form 3 Sine wave sweeping...

Page 10: ...Reliability 3 5 1 Nonrecoverable Read Errors The nonrecoverable read error rate will not exceed one sector in the specified number of bits read In the extremely unlikely event of a nonrecoverable read...

Page 11: ...Power On Off Cycles Defined as power being removed from the drive and then restored Most host systems remove power from the drive when entering suspend and hibernate as well as on a system shutdown 3...

Page 12: ...SATA SSD Notes 1 Connector Outline The 1 8 Intel X18 M SATA SSD connector is compliant to the SATA Rev 2 6 specifications 2 Connector Location The 1 8 Intel X18 M SATA SSD connector is compliant to t...

Page 13: ...765 008US 13 Intel X18 M X25 M SATA SSD 4 2 1 8 8 mm Intel X18 M SATA SSD The following figure shows the physical package information for the 8 mm deep 1 8 Intel X18 M SATA SSD Note All dimensions are...

Page 14: ...Order Number 319765 008US Intel X18 M X25 M SATA SSD 4 3 2 5 7 mm Intel X25 M SATA SSD The following figure shows the physical package information for the 7 mm deep 2 5 Intel X25 M SATA SSD Note All d...

Page 15: ...008US 15 Intel X18 M X25 M SATA SSD 4 4 2 5 9 5 mm Intel X25 M SATA SSD The following figure shows the physical package information for the 9 5 mm deep 2 5 Intel X25 M SATA SSD Note All dimensions ar...

Page 16: ...mber 319765 008US Intel X18 M X25 M SATA SSD 5 0 Pin and Signal Descriptions This section identifies the pin locations and signal descriptions of the Intel X18 M X25 M SATA SSDs 5 1 Pin Locations 5 1...

Page 17: ...er Segment P1 Table 13 Serial ATA Connector Pin Signal Definitions for 1 8 and 2 5 Form Factors Pin Function Definition S1 Ground 2nd mate S2 A Differential signal pair A S3 A S4 Ground 2nd mate S5 B...

Page 18: ...1st mate pins in both the power and signal connectors to discharge ESD in a suitably configured backplane connector 5 Power pins P7 P8 and P9 are internally connected to one another within the device...

Page 19: ...detection by a host system without hardware device detection 6 0 Command Sets 6 1 ATA Commands The Intel X18 M X25 M SATA SSDs support all the mandatory ATA commands defined in the ATA ATAPI 7 specif...

Page 20: ...irmware revision 8 ASCII characters 27 46 F Varies Model number Intel Solid State Drive 47 F 8010h 7 0 Maximum number of sectors transferred per interrupt on MULTIPLE commands 48 F 0h Reserved 49 F 2F...

Page 21: ...hanced security erase completion 91 V 0h Current advanced power management value 92 V FFFEh Master Password Revision Code 93 F 0h Hardware reset result The contents of bits 12 0 of this word shall cha...

Page 22: ...rts the Power Management command set which consists of CHECK POWER MODE IDLE IDLE IMMEDIATE SLEEP STANDBY STANDBY IMMEDIATE 120 F 401Ch Command Set Feature Enabled Supported 121 126 F 0h Reserved 127...

Page 23: ...and set which consists of SMART ENABLE OPERATIONS SMART DISABLE OPERATIONS SMART ENABLE DISABLE AUTOSAVE SMART RETURN STATUS The Intel X18 M X25 M SATA SSDs also support the following optional command...

Page 24: ...he Device Configuration Overlay command set which consists of DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTITY DEVICE CONFIGURATION RESTORE DEVICE CONFIGURATION SET 6 1 8 General Purpose...

Page 25: ...tor http www sffcommittee org June 2007 Intel Matrix Storage Manager http support intel com support chipsets imsm February 2007 Serial ATA Revision 2 6 http www sata io org May 2006 SFF 8223 2 5 Drive...

Page 26: ...ss Memory EXT Extended FP First Party GB Giga byte defined as 1x109 bytes HCI Host Controller Interface HCT Hardware Compatibility Test HDD Hard Disk Drive Host Initiated Link Power Management The abi...

Page 27: ...ata is copied to its permanent storage location VCCI Voluntary Control Council for Interface Table 18 Glossary of Terms and Acronyms Continued Term Definition Date Revision Description May 2009 008 Up...

Page 28: ...page 1 Modified Weights for different form factors on page 1 Modified Shock Spec on page 1 and Table 10 Shock and Vibration Specifications Updated Active and Idle Power number on Table 8 Typical Power...

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