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Intel® Server Board S2600WF Product Family Technical Product Specification 

120 

   

Appendix B.

 

POST Code Diagnostic LED Decoder 

As an aid in troubleshooting a system hang that occurs during a system POST process, the server board 

includes a bank of eight POST code diagnostic LEDs on the back edge of the server board. 
During the system boot process, Memory Reference Code (MRC) and system BIOS execute a number of 

memory initialization and platform configuration processes, each of which is assigned a hex POST code 

number. 
As each routine is started, the given POST code number is displayed to the POST code diagnostic LEDs on 

the back edge of the server board. 
During a POST system hang, the displayed POST code can be used to identify the last POST routine that was 

run prior to the error occurring, helping to isolate the possible cause of the hang condition. 
Each POST code is represented by eight LEDs, four green and four amber. The POST codes are divided into 

two nibbles, an upper nibble and a lower nibble. The upper nibble bits are represented by amber diagnostic 

LEDs and the lower nibble bits are represented by green diagnostics. If the bit is set in the upper and lower 

nibbles, the corresponding LED is lit. If the bit is clear, the corresponding LED is off. For each set of nibble 

bits, LED 0 represents the least significant bit (LSB) and LED 3 represents the most significant bit (MSB). 

 

Figure 75. Onboard POST diagnostic LED location and definition 

Note: Diagnostic LEDs are best read and decoded when viewing the LEDs from the back of the system. 

In the following example, the BIOS sends a value of 

AC

 to the diagnostic LED decoder. The LEDs are decoded 

as shown in Table 52, where the upper nibble bits represented by the amber LEDs equal 1010

b

 or A

and the 

lower nibble bits represented by the green LEDs equal 1100

b

 or C

h

. The two are concatenated as AC

h

Table 52. POST progress code LED example 

Upper Nibble 

Lower Nibble 

LED 3 

(MSB)  LED 2 

LED 1 

LED 0 

(LSB) 

Binary 

Code 

Hex 

Code 

LED 3 

(MSB) 

LED 2 

LED 1 

LED 0 

(LSB) 

Binary 

Code 

Hex 

Code 

ON 

off 

ON 

off 

1010 

ON 

ON 

off 

off 

1100 

 

Upper Nibble 

(amber) 

(Read first) 

Lower Nibble 

(green) 

(Read second) 

8h 

1h 

2h 

4h 

8h 

1h 

2h 

4h 

Summary of Contents for S2600WF Series

Page 1: ...Server Products and Solutions Intel Server Board S2600WF Product Family Technical Product Specification An overview of product features functions architecture and support specifications Rev 1 1 Octobe...

Page 2: ...Intel Server Board S2600WF Product Family Technical Product Specification Blank Page...

Page 3: ...duction Release October 2017 1 1 Updated all tables from Appendix B and Appendix C Updated Product Architecture Overview Updated S2600WF Architecture Block Diagram Added Intel QAT information Server B...

Page 4: ...t The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request...

Page 5: ...Xeon Processor Scalable Family with Integrated Intel Omni Path Fabric 39 3 3 3 Intel Omni Path IFT Carrier Accessory Kits 41 3 4 Processor Population Rules 44 3 5 Processor Initialization Error Summar...

Page 6: ...78 6 7 2 Onboard Video and Add In Video Adapter Support 79 6 7 3 Dual Monitor Support 79 7 Onboard Connector Header Pinout Definition 80 7 1 Power Connectors 80 7 1 1 Main Power 80 7 1 2 Hot Swap Bac...

Page 7: ...mware Force Update Jumper Block 106 11 4 BMC Force Update Jumper Block 107 11 5 BIOS Recovery Jumper 107 12 Platform Management 109 12 1 Management Feature Set Overview 109 12 1 1 IPMI 2 0 Features Ov...

Page 8: ...ix C POST Code Errors 126 C 1 POST Error Beep Codes 133 Appendix D Statement of Volatile Memory Components 134 Appendix E Supported Intel Server Systems 136 E 1 Intel Server System R1000WF Product Fam...

Page 9: ...he processor heat sink installation 34 Figure 16 PHM to CPU socket orientation and alignment features 34 Figure 17 Processor socket assembly and protective cover 35 Figure 18 Intel OP HFI connector lo...

Page 10: ...57 MAIN PWR 1 and MAIN PWR 2 connectors 80 Figure 58 Hot swap backplane power connector 82 Figure 59 Riser slot auxiliary power connectors 83 Figure 60 High power add in card 12 V auxiliary power cabl...

Page 11: ...ser card slot description 59 Table 19 Low profile riser card slot description 59 Table 20 Supported Intel Ethernet Network Adapters for OCP 60 Table 21 Intel VROC upgrade key options 67 Table 22 SATA...

Page 12: ...es overview 91 Table 47 System status LED states 99 Table 48 BMC boot reset status LED indicators 99 Table 49 Power control sources 111 Table 50 ACPI power states 111 Table 51 Component fault LEDs 118...

Page 13: ...the following table are classified as Intel Confidential These documents are made available under a Non Disclosure Agreement NDA with Intel and must be ordered through your local Intel representative...

Page 14: ...server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and operating environment Intel Corporation can...

Page 15: ...ver Board S2600WF is a monolithic printed circuit board assembly with features that are intended for high density 1U and 2U rack mount servers This server board is designed to support the Intel Xeon p...

Page 16: ...gure 2 Intel Server Board S2600WF with available onboard options Support for dual hot swap power supply modules 1 0 1 1 2 0 configurations Support for Intel Integrated SAS RAID module options Support...

Page 17: ...emory capacity o Up to 1 5 TB for Gold and Platinum CPUs o Up to 768 GB for Silver and Bronze CPUs Memory data transfer rates o Up to 2666 MT s at 1 and 2 DIMMs per channel dependent on processor DDR4...

Page 18: ...2 slot riser card available Video Integrated 2D video controller 16MB of DDR4 video memory 1 DB 15 external connector 1 14 pin internal connector for optional front panel video support USB 3 external...

Page 19: ...Product Specification 19 2 2 Server Board Component Feature Identification Figure 3 Server board component feature identification Note Intel Server Board S2600WFT shown Some features may not be prese...

Page 20: ...tion 20 Figure 4 Intel Server Board S2600WF external I O connector layout Figure 5 Intel Light Guided Diagnostics DIMM fault LEDs A RJ45 network port NIC 1 B RJ45 network port NIC 2 C Video D RJ45 ser...

Page 21: ...tel Server Board S2600WF Product Family Technical Product Specification 21 Figure 6 Intel Light Guided Diagnostic LED identification Note See Appendix B for POST Code Diagnostic LED decoder informatio...

Page 22: ...Intel Server Board S2600WF Product Family Technical Product Specification 22 Figure 7 Board configuration and recovery jumpers For more information on reset and recovery jumpers see Section 11...

Page 23: ...Intel Server Board S2600WF Product Family Technical Product Specification 23 2 3 Server Board Mechanical Drawings Figure 8 Intel Server Board S2600WF primary side keepout zone...

Page 24: ...Intel Server Board S2600WF Product Family Technical Product Specification 24 Figure 9 Intel Server Board S2600WF hole and component positions...

Page 25: ...Intel Server Board S2600WF Product Family Technical Product Specification 25 Figure 10 Intel Server Board S2600WF secondary side keepout zone...

Page 26: ...Intel Server Board S2600WF Product Family Technical Product Specification 26 Figure 11 Intel Server Board S2600WF primary side height restrictions...

Page 27: ...functions of the Intel Xeon processor Scalable family the Intel C620 series chipset PCH Intel Ethernet Controller X557 AT2 S2600WFT only and the ASPEED AST2500 baseboard management controller BMC Figu...

Page 28: ...FRU and sensor data record SDR data Together they configure and manage features and functions of the server system Many features and functions of the server system are managed jointly by the system B...

Page 29: ...ial system integration process system integrators must program system configuration data onto the server board using the FRUSDR utility to ensure the embedded platform management subsystem is able to...

Page 30: ...d and allows a manual selection of the desired boot device When an administrator password is installed in the BIOS setup utility the administrator password is required to access the boot pop up menu I...

Page 31: ...nt is logged to the SEL From the UEFI shell the BIOS can then be updated using a standard BIOS update procedure defined in update instructions provided with the system update package downloaded from t...

Page 32: ...is not installed 2 5 2 1 Loading FRU and SDR Data The FRU and SDR data can be updated using a standalone FRUSDR utility in the UEFI shell or can be done using the OFU utility program under a supporte...

Page 33: ...cooling capabilities of the chosen server chassis Check the server chassis or server system product specifications to determine maximum supported processor TDP Visit http www intel com support for a c...

Page 34: ...4 Figure 15 Processor attached to the processor heat sink installation Two bolster plate guide pins of different sizes allows the PHM to be installed only one way onto the processor socket assembly se...

Page 35: ...r 3 2 Processor Thermal Design Power TDP Support To allow optimal operation and long term reliability of Intel processor based systems the processor must remain within the defined minimum and maximum...

Page 36: ...select SKUs 768 GB 1 5 TB select SKUs 768 GB 768 GB RAS Capability Advanced Advanced Advanced Standard Standard Intel Turbo Boost Technology Yes Yes Yes Yes No Intel HT Technology Yes Yes Yes Yes No...

Page 37: ...o dynamically adjust processor voltage and core frequency as needed to enable decreased power consumption and decreased heat production All controls for transitioning between states are centralized wi...

Page 38: ...Advanced Encryption Standard The IntelAES NI feature includes six additional SIMD instructions in the Intel Streaming SIMD Extensions Intel SSE instruction set The BIOS is responsible in POST to detec...

Page 39: ...after booting An external agent can dynamically use or not use cores in the processor subsystem by requesting Intel ME Intel NM to control them specifying the number of cores to use or not use For ad...

Page 40: ...hin the OCP module bay A second cable carrying Intel Omni Path side band signals is connected between the IFT carrier board and sideband connectors on the server board External cables attach the IFT c...

Page 41: ...abric Processor Carriers AWF1PFABKITP Intel IFT Carrier Kit PCIe 1 Dual Port IFT Carrier PCIe Add in Card 1 Internal Omni Path Cable CPU1 1 Internal Omni Path Cable CPU2 1 Internal Omni Path Sideband...

Page 42: ...ssor sideband connector on the server board The sideband connectors are shown in Figure 22 Figure 22 Server board sideband connectors Each IFT carrier port has one green status LED as shown in Figure...

Page 43: ...for QSFP modules Power Level Class Max Power W 1 1 5 2 2 0 3 2 5 4 3 5 The server board has support for processor configurations where one or two installed processors may have an Intel OP HFI In dual...

Page 44: ...Fabric cannot be mixed Processors with different core frequencies can be mixed in a system given that the prior rules are met If this condition is detected all processor core frequencies are set to th...

Page 45: ...Fatal Halts at POST code 0xE5 Halts with three long beeps and one short beep Takes fatal error action see above and does not boot until the fault condition is remedied Processor cache or home agent no...

Page 46: ...on the screen Takes major error action The system may continue to boot in a degraded state depending on the POST Error Pause setting in setup or may halt with the POST error code in the error manager...

Page 47: ...erver board supports the following DDR4 DIMMs only Registered DIMMs RDIMMs Load Reduced DIMMs LRDIMMs and NVDIMMs Non Volatile Dual Inline Memory Module Only Error Correction Code ECC enabled RDIMMs o...

Page 48: ...may be functional Intel only supports and performs platform validation on systems that are configured with identical DIMMs installed On the Intel Server Board S2600WF a total of 24 DIMM slots are pro...

Page 49: ...possible When populating a quad rank DIMM with a single or dual rank DIMM in the same channel the quad rank DIMM must be populated farthest from the processor Incorrect DIMM placement results in an M...

Page 50: ...f channels A thru C 4 DIMM configurations DIMMs should be populated to DIMM slot 1 blue slots of channels A B D and E 5 DIMM configurations Not recommended This is an unbalanced configuration that yie...

Page 51: ...f the contents of memory as a redundant backup for use if the primary memory fails The mirrored copy of the memory is stored in memory of the same processor socket s IMC Dynamic without reboot failove...

Page 52: ...and the memory configuration is not able to support it during boot the system will fall back to independent channel mode and log and display errors Rank sparing mode is only possible when all channel...

Page 53: ...d Allocation The BIOS assigns PCI bus numbers in a depth first hierarchy in accordance with the PCI Local Bus Specification Revision 3 0 The bus number is incremented when the BIOS encounters a PCI PC...

Page 54: ...nly supports one configuration connection model NT Port attached to another NT Port of the same component type and generation The NTB provides Direct Address Translation between the two PCIe Hierarchi...

Page 55: ...rver Board S2600WF product family only the S2600WFQ SKU supports Intel QAT Intel QAT provides security and compression acceleration capabilities used to improve performance and efficiency across the d...

Page 56: ...rovides three riser card slots identified as Riser Slot 1 Riser Slot 2 and Riser Slot 3 Per the PCIe specification each riser card slot can support a maximum 75 W of power The PCIe bus lanes for each...

Page 57: ...2D x16 elec x16 mech Middle CPU 2 Ports 2C and 2D x8 elec x16 mech N A Bottom CPU 2 Ports 1A and 1B x8 elec x8 mech CPU 2 Ports 1A and 1B x8 elec x8 mech Table 15 Riser slot 3 PCIe root port mapping...

Page 58: ...ith other installed devices on the server board Figure 30 1U one slot PCIe riser card iPC F1UL16RISER3APP Table 16 One slot PCIe riser card slot description Slot Description Slot 1 PCIe x16 elec x16 m...

Page 59: ...CIe x8 elec x8 mechanical 6 2 2 Riser Slot 3 Riser Card Option iPC A2UX8X4RISER Riser slot 3 is provided to support up to two additional PCIe add in card slots for 2U server configurations The availab...

Page 60: ...Adapter for OCP connector Table 16 lists the supported OCP modules Table 20 Supported Intel Ethernet Network Adapters for OCP Description iPC Quad Port 1GB RJ45 I357T4OCPG1P5 Quad Port SFP X527DA4OCP...

Page 61: ...oard Storage Subsystem The Intel Server Board S2600WF product family includes support for many storage related technologies and onboard features to support a wide variety of storage options These incl...

Page 62: ...rd mounted M 2 SSDs is defined as follows Neither Intel ESRT2 nor Intel RSTe have RAID support for PCIe M 2 SSDs when installed to the M 2 connectors on the server board Note NVMe RAID support using I...

Page 63: ...evice Intel VMD is hardware logic inside the processor root complex to help manage PCIe NVMe SSDs It provides robust hot plus support and status LED management This allows servicing of storage system...

Page 64: ...essor Intel VMD cannot provide device management on PCI lanes routed from the chipset PCH When Intel VMD is enabled the BIOS does not enumerate devices that are behind Intel VMD The Intel VMD enabled...

Page 65: ...Intel Server Board S2600WF Product Family Technical Product Specification 65 Figure 39 Intel VMD support disabled in BIOS setup Figure 40 Intel VMD support enabled in BIOS setup...

Page 66: ...allows recovery from a double fault Isolated storage devices from OS for error handling Protected R5 data from OS crash Boot from RAID volumes based on NVMe SSDs within a single Intel VMD domain NVMe...

Page 67: ...ent Note Intel VROC upgrade keys referenced in Table 21 are used for PCIe NVMe SSDs only For SATA RAID support see Section 6 3 6 6 3 5 Onboard SATA Support The server board utilizes two chipset embedd...

Page 68: ...ed and ability to connect and disconnect devices without prior notification to the system Supported Supported Asynchronous Signal Recovery Provides a recovery from a loss of signal or establishing com...

Page 69: ...ined startup power demand surge for all drives at once can be much higher than the normal running power requirements and could require a much larger power supply for startup than for normal operations...

Page 70: ...RAID 10 A combination of RAID 0 and RAID 1 consists of striped data across mirrored spans It pro vides high data throughput and complete data redundancy but uses a larger number of spans By using Inte...

Page 71: ...ID support for PCIe NVMe SSDs Intel ESRT2 is based on LSI MegaRAID software stack and utilizes the system memory and CPU Supported RAID levels include RAID 0 Uses striping to provide high data through...

Page 72: ...ection when on and transmit receive activity when blinking The LED on the right side of the connector indicates link speed Table 24 provides a full definition for the LED states Figure 47 RJ45 connect...

Page 73: ...es 6 5 Serial Port Support The server board has support for two serial ports Serial A and Serial B Serial A is an external RJ45 type connector located on the back edge of the server board as shown in...

Page 74: ...r labeled Serial_B on the server board The connector location is shown in Figure 50 and the pinout is given in Table 26 Figure 50 Serial B connector internal Table 26 Serial B connector pinout Signal...

Page 75: ...ed USB 3 0 ports on the back edge of the server board Figure 51 External USB 3 0 ports 6 6 2 Internal USB 2 0 Type A Connector The server board includes one internal Type A USB 2 0 connector Figure 52...

Page 76: ...04_RXN USB3_01_RXN 18 3 USB3_04_RXP USB3_01_RXP 17 4 GROUND GROUND 16 5 USB3_04_TXN USB3_01_TXN 15 6 USB3_04_TXP USB3_01_TXP 14 7 GROUND GROUND 13 8 USB2_13_DN USB2_10_DN 12 9 USB2_13_DP USB2_10_DP 11...

Page 77: ...master support With 16 MB of memory reserved the video controller can support the resloutions specified in Table 29 Table 29 Supported video resolutions 2D Mode 2D Video Support Color Bit Resolution 8...

Page 78: ...rnal video connector On the server board near the front right edge is A connector near the front right edge of the server board labeled FP_VIDEO that when cabled can provide video from the front of th...

Page 79: ...d Some multi socket boards have PCIe slots capable of hosting an add in video card which are attached to the IIOs of CPU sockets other than CPU Socket 1 However only one CPU socket can be designated a...

Page 80: ...s Processor sockets 7 1 Power Connectors The server board includes several power connectors that are used to provide DC power to various devices 7 1 1 Main Power Main server board power is supplied fr...

Page 81: ...A18 P12V P3V3_AUX PD_PS1_FRU_A0 B19 A19 SMB_PMBUS_DATA_R P3V3_AUX PD_PS1_FRU_A1 B20 A20 SMB_PMBUS_CLK_R P12V_STBY B21 A21 FM_PS_EN_PSU_N FM_PS_CR1 B22 A22 IRQ_SML1_PMBUS_ALERTR2_N P12V_SHARE B23 A23...

Page 82: ...2V_SENSE FM_PS_COMPATIBILITY_BUS B25 A25 PWRGD_PS_PWROK 7 1 2 Hot Swap Backplane Power Connector The server board includes one white 2x6 pin power connector that when cabled provides power for hot swa...

Page 83: ...5 W but is also limited by available power provided by the power supply and the total power draw of the given system configuration A power budget for the complete system should be performed to determi...

Page 84: ...ntended to provide power for peripheral devices such as optical disk drives ODDs and or solid state devices SSDs On the server board this connector is labeled as Peripheral_ PWR Table 35 provides the...

Page 85: ...panel header labeled FRONT_PANEL and a custom high density 30 pin front panel connector labeled STORAGE _FP Figure 62 Front control panel connectors Supported control buttons and LEDs are identified...

Page 86: ...ystem The power LED is a single color and is capable of supporting different indicator states as defined in Table 38 Table 38 Power sleep LED functional states Power Mode LED System State Description...

Page 87: ...rol panel includes an activity LED indicator for each onboard NIC When a network link is detected the LED lights up constantly The LED begins to blink once network activity occurs at a rate that is co...

Page 88: ...gure 64 Dual rotor fixed mount fan pin connector orientation Table 40 Dual rotor fixed mount fan connector pinout Signal Description Pin LED_FAN 10 LED_FAN_FAULT 9 SYS FAN PRSNT 8 GROUND 7 GROUND 6 FA...

Page 89: ...eral management interface connectors Table 42 Table 43 and Table 44 provide the pinout definition for each Figure 67 Hot swap backplane connector locations Table 42 Hot swap backplane I2 C connector S...

Page 90: ...amily Technical Product Specification 90 Table 43 Hot swap backplane I2 C connector SMBUS 4 pin J1K1 Pin Signal 1 SDA 2 Ground 3 SCL 4 RST_PCIE_SSD_PERST Table 44 IPMB SMBUS 4 pin J1C3 Pin Signal 1 CM...

Page 91: ...rd video and mouse KVM and media redirection On the server board the Intel RMM4 Lite key is installed at the location shown in Figure 68 Figure 68 Intel RMM4 Lite activation key installation When the...

Page 92: ...zable web GUI which exposes the manageability features of the BMC base feature set It is supported over all onboard NICs that have management connectivity to the BMC as well as an optional dedicated a...

Page 93: ...ssion after a user configurable inactivity period By default this inactiv ity period is 30 minutes Provide embedded platform debug feature allowing the user to initiate a debug dump to a file that can...

Page 94: ...embedded web server as a Java applet This feature is only enabled when the Intel RMM4 Lite is present The client system must have a Java Runtime Environment JRE version 6 0 or later to run the KVM or...

Page 95: ...USB CD ROM floppy drive or a USB flash disk as a remote device to the server Once mounted the remote device appears to the server just like a local device allowing system administrators or users to in...

Page 96: ...the administration forms displayed by the browser The remote console window is a Java applet that establishes TCP connections to the BMC The protocol that is run over these connections is a unique KV...

Page 97: ...Specification 97 9 Light Guided Diagnostics The server board includes several onboard LED indicators to aid troubleshooting various board level faults Figure 70 and Figure 71 show the location for ea...

Page 98: ...present 9 2 System Status LED The server board includes a bi color system status LED The system status LED on the server board is tied directly to the system status LED on the front panel if present...

Page 99: ...ace and system loses memory redundancy 8 Battery failure 9 BMC executing in uBoot Indicated by Chassis ID blinking at 3Hz System in degraded state no manageability BMC uBoot is running but has not tra...

Page 100: ...started the BIOS displays the given POST code to the POST code diagnostic LEDs The purpose of these LEDs is to assist in troubleshooting a system hang condition during the POST process The diagnostic...

Page 101: ...usted Platform Module TPM support Intel Trusted Execution Technology Intel TXT 10 1 Password Protection The BIOS setup utility accessed during POST includes a Security tab where options to configure p...

Page 102: ...lt values by any method has no effect on the administrator and user passwords As a security measure if a user or administrator enters an incorrect password three times in a row during the boot sequenc...

Page 103: ...surements from multiple factors within the boot process to create a system fingerprint This unique fingerprint remains the same unless the pre boot environment is tampered with Therefore it is used to...

Page 104: ...ote that while using TPM a TPM enabled operating system or application may change the TPM state independently of the BIOS setup When an operating system modifies the TPM state the BIOS Setup displays...

Page 105: ...This jumper resets BIOS options configured using the F2 BIOS Setup Utility back to their original default factory settings Note This jumper does not reset administrator or user passwords To reset pass...

Page 106: ...rd clear operation was successful by viewing the Error Manager screen Two errors should be logged o 5221 Passwords cleared by jumper o 5224 Password clear jumper is set 7 Exit the BIOS setup utility a...

Page 107: ...ords Note If the BMC FRC UPD jumper is moved with AC power applied to the system the BMC will not operate properly 2 Remove the system top cover 3 Move the BMC FRC UPD jumper from pins 1 2 default to...

Page 108: ...following steps 1 Turn off the system and remove the AC power cords 2 Remove the system top cover 3 Move the BIOS Recovery jumper from pins 1 2 default to pins 2 3 BIOS recovery position 4 Re install...

Page 109: ...tures is dependent on the server platform in which the server board is integrated and any additional system level components and options that may be installed 12 1 1 IPMI 2 0 Features Overview The bas...

Page 110: ...e readings Sending and responding to Address Resolution Protocols ARPs supported on embedded NICs Dynamic Host Configuration Protocol DHCP supported on embedded NICs Platform environment control inter...

Page 111: ...ds Routed through command processor Turns power on or off or power cycle Power state retention Implemented by means of BMC internal logic Turns power on when AC power returns Chipset Sleep S4 S5 signa...

Page 112: ...chdog timeout action The BIOS is responsible for disabling the FRB 2 timeout before initiating the option ROM scan and before displaying a request for a boot password If the processor fails and causes...

Page 113: ...m Sensors Sensors can be re armed either manually or automatically An automatic re arm sensor re arms clears the assertion event state for a threshold or offset if that threshold or offset is de asser...

Page 114: ...fixed but configurable through OEM SDRs fan speeds associated with them The nominal state has a variable speed determined by the fan domain policy An OEM SDR record is used to configure the fan domain...

Page 115: ...uty cycle which is the percentage of time the signal is driven high in each pulse The BMC controls the average duty cycle of each PWM signal through direct manipulation of the integrated PWM control r...

Page 116: ...Figure 74 High level fan speed control process 12 3 3 6 Fan Boosting Due to Fan Failures Each fan failure is able to define a unique response from all other fan domains An OEM SDR table defines the re...

Page 117: ...m the IMC are these estimated values 12 3 4 2 Dynamic Hybrid CLTT The system supports dynamic memory CLTT for which the BMC firmware dynamically modifies thermal offset registers in the IMC during run...

Page 118: ...hese LEDs are only active when the system is in the on state The BMC does not activate or change the state of the LEDs unless instructed by the BIOS HDD status LEDs The HSBP PSoC of supported Intel an...

Page 119: ...on the server board can only be used in dual processor configurations The riser card slots are specifically designed to support riser cards only Attempting to install a PCIe add in card directly into...

Page 120: ...nibble and a lower nibble The upper nibble bits are represented by amber diagnostic LEDs and the lower nibble bits are represented by green diagnostics If the bit is set in the upper and lower nibbles...

Page 121: ...ranks 1 0 0 0 0 0 0 0 1 Train DDR4 ranks 2 0 0 0 0 0 0 1 0 Train DDR4 ranks Read DQ DQS training 3 0 0 0 0 0 0 1 1 Train DDR4 ranks Receive enable training 4 0 0 0 0 0 1 0 0 Train DDR4 ranks Write lev...

Page 122: ...s locked by Intel TXT and is inaccessible EA 1 1 1 0 1 0 1 0 DDR4 channel training error 01h Error on read DQ DQS Data Data Strobe init 02h Error on Receive Enable 03h Error on Write Leveling 04h Erro...

Page 123: ...tion A8 1 0 1 0 1 0 0 0 Program final route A9 1 0 1 0 1 0 0 1 Program final IO SAD setting AA 1 0 1 0 1 0 1 0 Protocol layer and other uncore settings AB 1 0 1 0 1 0 1 1 Transition links to full spee...

Page 124: ...DXE USB detect 9D 1 0 0 1 1 1 0 1 DXE USB enable A1 1 0 1 0 0 0 0 1 DXE IDE begin A2 1 0 1 0 0 0 1 0 DXE IDE reset A3 1 0 1 0 0 0 1 1 DXE IDE detect A4 1 0 1 0 0 1 0 0 DXE IDE enable A5 1 0 1 0 0 1 0...

Page 125: ...0 0 0 1 S3 Resume PEIM S3 boot script E2 1 1 1 0 0 0 1 0 S3 Resume PEIM S3 Video Repost E3 1 1 1 0 0 0 1 1 S3 Resume PEIM S3 OS wake BIOS Recovery F0 1 1 1 1 0 0 0 0 PEIM which detected forced Recover...

Page 126: ...system continues booting in a degraded state The user may want to replace the erroneous unit The POST Error Pause option setting in the BIOS setup does not have any effect on this error Major An error...

Page 127: ...settings Major 5221 Passwords cleared by jumper Major 5224 Password clear jumper is Set Recommend to remind user to install BIOS password as BIOS admin password is the master keys for several BIOS se...

Page 128: ...52F Memory failed test initialization CPU1_DIMM_F1 please remove the disabled DIMM Major 8530 Memory failed test initialization CPU1_DIMM_F2 please remove the disabled DIMM Major 8531 Memory failed te...

Page 129: ...d CPU1_DIMM_G2 please remove the disabled DIMM Major 8554 Memory disabled CPU1_DIMM_G3 please remove the disabled DIMM Major 8555 Memory disabled CPU1_DIMM_H1 please remove the disabled DIMM Major 855...

Page 130: ...ory encountered a Serial Presence Detection SPD failure CPU1_DIMM_F3 Major 8572 Memory encountered a Serial Presence Detection SPD failure CPU1_DIMM_G1 Major 8573 Memory encountered a Serial Presence...

Page 131: ...CPU2_DIMM_H2 please remove the disabled DIMM Major 85CF Memory failed test initialization CPU2_DIMM_H3 please remove the disabled DIMM Major 85D0 Memory disabled CPU2_DIMM_C3 please remove the disabl...

Page 132: ...85EC Memory encountered a Serial Presence Detection SPD failure CPU2_DIMM_G3 Major 85ED Memory encountered a Serial Presence Detection SPD failure CPU2_DIMM_H1 Major 85EE Memory encountered a Serial...

Page 133: ...ry is initiated that it sounds like a 2 4 beep code The integrated BMC may generate beep codes upon detection of failure conditions Beep codes are sounded each time the problem is discovered such as o...

Page 134: ...Data The flash components on the server boards do not store user data from the operating sys tem No operating system level data is retained in any listed components after AC power is removed The persi...

Page 135: ...NO FW BMC Flash Non Volatile 4 Mbit U5M1 No 10 GB NIC EEPROM S2600WF Non volatile N A U1E3 No CPLD Volatile 512 MB U1D2 No BMC firmware SDRAM None volatile 8 GB U8N1 No BMC eMMC Note Table 59 does not...

Page 136: ...F product family and the Intel Server System R2000WF product family The sections below provide a high level overview of the features associated with each For additional product information refer to th...

Page 137: ...ule Riser Card Support Support for two riser cards Riser 1 PCIe 3 0 x24 Riser 2 PCIe 3 0 x24 With two riser cards installed up to two possible add in cards can be supported one x16 PCIe 3 0 add in car...

Page 138: ...tel Server Chassis R2208WFxxxx and R2308WFxxxx configurations only External I O Connections DB 15 video connectors o Front and back non storage system configurations only RJ 45 serial port A connector...

Page 139: ...3 5 SAS SATA 8 x 2 5 combo backplane SAS SATA NVMe 8 x 2 5 Dual Port SAS 12 x 3 5 SAS SATA supports up to 2 NVMe drives Note All available backplane options have support for SAS 3 0 12 Gb sec Storage...

Page 140: ...Light Emitting Diode LRDIMM Load Reduced DIMM LSB Least Significant Bit MSB Most Significant Bit NIC Network Interface Card NMI Non maskable Interrupt OCuLink Optical Copper Link PCI Peripheral Compo...

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