Intel R2000WF series, Technical Product Specification

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Intel® Server System R2000WF Product Family Technical Product Specification
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B.2. BIOS POST Progress Codes
The following table provides a list of all POST progress codes.
Table 79. POST progress codes
Checkpoint
Diagnostic LED Decoder
Description
1 = LED On, 0 = LED Off
Upper Nibble Lower Nibble
MSB LSB
8h 4h 2h 1h 8h 4h 2h 1h
LED # #7 #6 #5 #4 #3 #2 #1 #0
SEC Phase
1h 0 0 0 0 0 0 0 1 First POST code after CPU reset
2h 0 0 0 0 0 0 1 0 Microcode load begin
3h 0 0 0 0 0 0 1 1 CRAM initialization begin
4h 0 0 0 0 0 1 0 0 PEI Cache When Disabled
5h 0 0 0 0 0 1 0 1 SEC Core At Power On Begin.
6h 0 0 0 0 0 1 1 0 Early CPU initialization during SEC Phase.
KTI RC (fully leverage without platform change)
A1h 1 0 1 0 0 0 0 1 Collect infor such as SBSP, boot mode, reset type, etc.
A3h 1 0 1 0 0 0 1 1 Setup minimum path between SBSP and other sockets
A6h 1 0 1 0 0 1 1 0 Sync up with PBSPs
A7h 1 0 1 0 0 1 1 1 Topology discovery and route calculation
A8h 1 0 1 0 1 0 0 0 Program final route
A9h 1 0 1 0 1 0 0 1 Program final IO SAD setting
AAh 1 0 1 0 1 0 1 0 Protocol layer and other uncore settings
ABh 1 0 1 0 1 0 1 1 Transition links to full speed operation
AEh 1 0 1 0 1 1 1 0 Coherency settings
AFh 1 0 1 0 1 1 1 1 KTI initialization done
PEI Phase
10h 0 0 0 1 0 0 0 0 PEI Core
11h 0 0 0 1 0 0 0 1 CPU PEIM
15h 0 0 0 1 0 1 0 1 Platform Type Init
19h 0 0 0 1 1 0 0 1 Platform PEIM Init
31h 0 0 1 1 0 0 0 1 Memory Installed
32h 0 0 1 1 0 0 1 0 CPU PEIM (CPU Init)
33h 0 0 1 1 0 0 1 1 CPU PEIM (Cache Init)
34h 0 0 1 1 0 1 0 0 CPU BSP Select
35h 0 0 1 1 0 1 0 1 CPU AP Init
36h 0 0 1 1 0 1 1 0 CPU SMM Init
4Fh 0 1 0 0 1 1 1 1 DXE IPL started