Intel PXA270, Optimization Manual

Page: 22 / 144

2-2 Intel® PXA27x Processor Family Optimization Guide
Microarchitecture Overview
Table 2-1 gives a brief description of each pipe stage and a reference for further information.
2.2.1.2 Out of Order Completion
While the pipeline is scalar and single-issue, instructions occupy all three pipelines at once. The
main execution pipeline, memory, and MAC pipelines have different execution times because they
are not lock-stepped. Sequential consistency of instruction execution relates to two aspects: first,
the order instructions are completed and second, the order memory is accessed due to load and
store instructions. The Intel XScale® Microarchitecture only preserves a weak processor
consistency because instructions complete out of order (assuming no data dependencies exist).
The Intel XScale® Microarchitecture can buffer up to four outstanding reads. If load operations
miss the data cache, subsequent instructions complete independently. This operation is called a
hit-under-miss operation.
2.2.1.3 Use of Bypassing
The pipeline makes extensive use of bypassing to minimize data hazards. To eliminate the need to
stall the pipeline, bypassing allows results forwarding from multiple sources.
In certain situations, the pipeline must stall because of register dependencies between instructions.
A register dependency occurs when a previous MAC or load instruction is about to modify a
register value that has not returned to the register file. Core bypassing allows the current instruction
to execute when the previous instruction’s results are available without waiting for the register file
to update.
2.2.2 Instruction Flow Through the Pipeline
With the exception of the MAC unit, the pipeline issues one instruction per clock cycle. Instruction
execution begins at the F1 pipestage and completes at the WB pipestage.
Although a single instruction is issued per clock cycle, all three pipelines are processing
instructions simultaneously. If there are no data hazards, each instruction complete independently
of the others.
Table 2-1. Pipelines and Pipe Stages
Pipe / Pipestage Description For More Information
Main Execution Pipeline
• IF1/IF2
• ID
• RF
• X1
• X2
• XWB
Handles data processing instructions
Instruction Fetch
Instruction Decode
Register File / Operand Shifter
ALU Execute
State Execute
Write-back Section 2.2.3
Section 2.2.3.1
Section 2.2.3.2
Section 2.2.3.3
Section 2.2.3.4
Section 2.2.3.5
Section 2.2.3.6
Memory Pipeline
• D1/D2
• DWB
Handles load/store instructions
Data cache access
Data cache writeback Section 2.2.4
Section 2.2.4.1
Section 2.2.5.1
MAC Pipeline
• M1-M5
• MWB (not shown)
Handles all multiply instructions
Multiplier stages
MAC write-back occurs during M2-M5 Section 2.2.5
Section 2.2.5
Section 2.2.5