Intel PENTIUM P6000 SPECIFICATION 20 Specification Download Page 1

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Document Number: 323874-002

Intel® Pentium® P6000 and U5000

Mobile Processor Series

Specification Update

June 2010

Revision 002

Summary of Contents for PENTIUM P6000 SPECIFICATION 20

Page 1: ...Document Number 323874 002 Intel Pentium P6000 and U5000 Mobile Processor Series Specification Update June 2010 Revision 002...

Page 2: ...eristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising...

Page 3: ...Specification Update 3 Contents Preface 5 Summary Tables of Changes 7 Identification Information 15 Errata 17 Specification Changes 45 Specification Clarifications 46 Documentation Changes 47...

Page 4: ...4 Specification Update Revision History Revision Description Revision Date 001 Initial release May 2010 002 Added P6000 sku information June 2010...

Page 5: ...s documentation Document Title Document Number Location Intel Pentium P6000 and U5000 Mobile Processor Series Datasheet 323873 Intel Core i7 600 i5 500 i5 400 and i3 300 Mobile Processor Series Datash...

Page 6: ...release of the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications wi...

Page 7: ...ification that applies to this stepping No mark or Blank box This erratum is fixed in listed stepping or specification change does not apply to listed stepping Page Page Page location of item in this...

Page 8: ...n process in Micro FCPGA package W Intel Celeron M processor X Intel Pentium M processor on 90 nm process with 2 MB L2 cache and Intel processor A100 and A110 with 512 KB L2 cache Y Intel Pentium M pr...

Page 9: ...or AAC Intel Celeron dual core processor E1000 series AAD Intel Core 2 Extreme processor QX9775 AAE Intel Atom processor Z5xx series AAF Intel Atom processor 200 series AAG Intel Atom processor N seri...

Page 10: ...with Floating Point Exception Pending May Be Mishandled BG10 X X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame BG11 X X No Fix IRET under Certain Conditions May Cau...

Page 11: ...Cores in Deep Power Down Technology code name C6 state BG30 X X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur BG31 X X No Fix EOI Transaction May Not Be Sent If Software Enters Core...

Page 12: ...flow of IA32_FIXED_CTR2 BG52 X X No Fix LBRs May Not be Initialized During Power On Reset of the Processor BG53 X X No Fix LBR BTM or BTS Records May Have Incorrect Branch From Information After an En...

Page 13: ...ith Interrupt Acknowledge Cycle From the Preceding Interrupt BG72 X Fixed CPUID Incorrectly Reports a C State as Available When this State is Unsupported BG73 X X No Fix The Combination of a Page Spli...

Page 14: ...cation Changes None for this revision of this specification update Specification Clarifications Number Specification Clarifications None for this revision of this specification update Documentation Ch...

Page 15: ...gister accessible through Boundary Scan 6 The Stepping ID in bits 3 0 indicates the revision number of that model See above table for the processor stepping ID number in the CPUID information When EAX...

Page 16: ...processor BGA Component Markings Table 1 1 Processor Identification QDF16 S Spec Number Processor Number Stepping Processor Signature Host Device ID Host Revision ID L3 Cache MB Frequency Max Intel T...

Page 17: ...ing Operations in Pentium 4 Intel Xeon and P6 Family Processors the processor performs REP MOVS or REP STOS as fast strings Due to this erratum fast string REP MOVS REP STOS instructions that cross pa...

Page 18: ...to a non canonical address the address pushed onto the stack for this GP fault may not match the non canonical address that caused the fault Implication Operating systems may observe a GP fault being...

Page 19: ...may issue a memory load before getting the DNA exception Workaround Code which performs loads from memory that has side effects can effectively workaround this behavior by using simple integer based...

Page 20: ...from SMM System Management Mode the CPU will incorrectly update the LBR Last Branch Record and the BTS Branch Trace Store hence rendering their data invalid The corresponding data if sent out as a BTM...

Page 21: ...y commercially available software Workaround None identified Status For the steppings affected see the Summary Tables of Changes BG11 IRET under Certain Conditions May Cause an Unexpected Alignment Ch...

Page 22: ...00000000h that occur above the 4 G limit 0ffffffffh may not signal a GP fault Implication When such memory accesses occur in 32 bit mode the system may not issue a GP fault Workaround Software should...

Page 23: ...cause the lower two bits of CS segment register to be corrupted Implication The corruption of the bottom two bits of the CS segment register will have no impact unless software explicitly examines th...

Page 24: ...descriptor straddles the canonical boundary the error code pushed onto the stack may be incorrect Implication An incorrect error code may be pushed onto the stack Intel has not observed this erratum w...

Page 25: ...Software Developer s Manual the use of MOV SS POP SS in conjunction with MOV r e SP r e BP will avoid the failure since the MOV r e SP r e BP will not generate a floating point exception Developers o...

Page 26: ...ependently Implication Software can not rely on synchronous reset of the IA32_APERF IA32_MPERF registers Workaround None identified Status For the steppings affected see the Summary Tables of Changes...

Page 27: ...nges BG27 xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in Periodic Mode Problem When the xAPIC Timer is automatically reloaded by counting down to zero in periodic mode th...

Page 28: ...d while counting down the current count reaches 1 at the same time that the processor thread begins a transition to a low power C state the xAPIC may generate two interrupts instead of the expected on...

Page 29: ...received on the same internal clock that the ESR is being written as part of the write read ESR access flow The corresponding error interrupt will also not be generated for this case Implication Due t...

Page 30: ...ack retired instructions which contain a store operation Due to this erratum the processor may also count other types of instructions including WRMSR and MFENCE Implication Performance Monitoring coun...

Page 31: ...her than expected Workaround Software should ensure this event is only enabled while in EPT mode Status For the steppings affected see the Summary Tables of Changes BG41 Memory Aliasing of Code Pages...

Page 32: ...t values and must be enabled in IA32_PERF_GLOBAL_CTRL MSR 38FH bits 3 0 All three values must be written to either the same or different IA32_PERFEVTSELx MSRs before programming the performance counte...

Page 33: ...e x stands for zero or one and a yellow threshold based error status indication bits 54 53 equal to 10B may be overwritten by a corrected error with a no tracking indication 00B or green indication 01...

Page 34: ...set Implication Software may not operate properly if it relies on the processor to deliver page faults when reserved bits are set in paging structure entries Workaround Software should not set Bit 7...

Page 35: ...errupts may be unexpectedly generated Workaround None identified Status For the steppings affected see the Summary Tables of Changes BG52 LBRs May Not Be Initialized during Power On Reset of the Proce...

Page 36: ..._BLOCKS NOT_STA and STORE_BLOCKS STA may indicate a higher occurrence of loads blocked by stores than have actually occurred If Intel Hyper Threading Technology is enabled the counts of loads blocked...

Page 37: ...anges BG58 LER MSRs May Be Unreliable Problem Due to certain internal processor events updates to the LER Last Exception Record MSRs MSR_LER_FROM_LIP 1DDH and MSR_LER_TO_LIP 1DEH may happen when no up...

Page 38: ...Instruction that Re maps a Page May Encounter an Unexpected Page Fault Problem An unexpected page fault PF may occur for a page under the following conditions Implication Software may see an unexpecte...

Page 39: ...arding the duplicate TLP Note The duplicate packet can be received only as a result of a correctable error in the other end point Transmitter Implication The processor does not comply with the PCI Exp...

Page 40: ...6 state Exit Problem In a complex set of internal conditions an internal parity error may occur during a Core Deep Power Down Technology code name C6 state exit Implication Due to this erratum an unco...

Page 41: ...owledge for the previous External Interrupt arrive at the APIC at the same time Implication Due to this erratum any further 8259 Virtual Wire B Mode External Interrupts will subsequently be ignored Wo...

Page 42: ...for an SMI Handler to determine the source of the SMI Software that relies on the IO_SMI bit in SMM save state or synchronous SMI behavior may not function as expected Workaround A BIOS workaround has...

Page 43: ...ile the APIC timer countdown is in progress Implication Due to this erratum certain software may incorrectly assess that the APIC timer countdown is complete when it is actually still running This err...

Page 44: ...ore report incorrect counts This erratum may affect event codes in the ranges 00H to 0CH and 40H to 43H Implication Due to this erratum the count value for some uncore Performance Monitoring Events ma...

Page 45: ...Specification Update 45 Specification Changes Specification Changes There are no new Specification Changes in this Specification Update revision...

Page 46: ...Specification Clarifications 46 Specification Update Specification Clarifications There are no new Specification Clarifications in this Specification Update revision...

Page 47: ...Specification Update 47 Documentation Changes Documentation Changes There are no new Document Changes in this Specification Update revision...

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