Datasheet
73
Signal Description
6.3
Reset and Miscellaneous Signals
Table 6-25.Reset and Miscellaneous Signals (Sheet 1 of 2)
Signal Name
Description
Direction/Buffer
Type
SM_DRAMRST#
DDR3 DRAM Reset:
Reset signal from
processor to DRAM devices. One for all
channels or SO-DIMMs.
O
DDR3
PM_EXT_TS#[0]
PM_EXT_TS#[1]
External Thermal Sensor Input:
If the
system temperature reaches a dangerously
high value then this signal can be used to
trigger the start of system memory
throttling.
I
CMOS
COMP0
Impedance compensation must be
terminated on the system board using a
precision resistor.
I
A
COMP1
Impedance compensation must be
terminated on the system board using a
precision resistor.
I
A
COMP2
Impedance compensation must be
terminated on the system board using a
precision resistor.
I
A
COMP3
Impedance compensation must be
terminated on the system board using a
precision resistor.
I
A
PM_SYNC
Power Management Sync:
A sideband
signal to communicate power management
status from the platform to the processor.
I
CMOS
RESET_OBS#
This signal is an indication of the processor
being reset.
O
Asynchronous CMOS
RSTIN#
Reset In:
When asserted this signal will
asynchronously reset the processor logic.
This signal is connected to the PLTRST#
output of the PCH.
I
CMOS
BPM#[7:0]
Breakpoint and Performance Monitor
Signals:
Outputs from the processor that
indicate the status of breakpoints and
programmable counters used for monitoring
processor performance.
I/O
GTL
DBR#
Debug Reset:
Used only in systems where
no debug port is implemented on the system
board. DBR# is used by a debug port
interposer so that an in-target probe can
drive system reset. This signal only routes
through the package and does not connect to
the the processor silicon itself.
O
