Intel PCH-LP, Programming Manual

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Intel Confidential
PCH SPI Flash Architecture
2 PCH SPI Flash Architecture
PCH SPI interface consists of clock (CLK), MOSI (Master Out Slave In) MISO (Master In
Slave Out),IO2, IO3 (For Quad Fast Read and Quad I/O support) and up to 3 active low
chip selects (CSX#) on Intel ® microarchitecture code name Broadwell PCH-LP. Chip
Select 3 (CS3#) is dedicated for Intel TPM on SPI usage.
Broadwell PCH-LP Family can support SPI flash devices up to 64 Bytes per chip select
and frequencies of 20 MHz, 33 MHz, and 50 MHz.
2.1 Descriptor Mode
Descriptor mode supports up to two SPI flashes. It allows integrated LAN support, as
well as Intel
®
ME firmware to share flash. There is also additional security for reads and
writes to the flash. Hardware sequencing, heterogeneous flash space, Intel integrated
LAN, Intel
®
ME firmware on SPI flash, require descriptor mode. Descriptor mode
requires the SPI flash to be hooked up directly to the PCH’s SPI bus.
See SPI Supported Feature Overview of the latest Intel Platform Controller Hub
Family External Design Specification (EDS) for Broadwell PCH-LP (Wildcat Point-LP)
Family for more detailed information.
2.2 Serial Flash Discoverable Parameter (SFDP)
Broadwell PCH-LP supports SPI with SFDP. SFDP (Serial Flash Discoverable Parameter)
is a JEDEC standard provides a consistent method of describing the functional and
feature capabilities of SPI devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by PCH to enable adjustment needed to
accommodate divergent feature from multiple vendors.
Please refer to Chapter 5, “Serial Flash Discoverable Parameter (SFDP) Overview” for
more information.
2.3 SPI Fast Read
Broadwell PCH-LP Family supports SPI Dual output, Dual I/O, Quad output and
Quad I/O Fast read instruction with frequencies 20, 33, and 50 MHz.
Note: 50-MHz support requires SPI component that meet 66-MHz timing.
2.4 Intel
®
TPM on SPI Bus
Broadwell PCH-LP Family supports Intel TPM on the SPI bus. Intel TPM attached to the
system may be using LPC or SPI. SPI Intel TPM is accessed much like direct reads and
direct writes.
2.5 Boot Destination Option
2.5.1 Boot Flow for Broadwell PCH-LP Family
When booting from Global Reset, the PCH SPI controller will check whether the SPI
component is supporting SFDP by sending 5Ah to SPI to CS0 first then CS1. SFDP
fetching will triggered when assertion of MEPWROK. If the SPI has a valid SFDP, the
controller supports auto discovery of the Component Property Parameter Table (CPPT)