A Detailed Look Inside the Intel
®
NetBurst
™
Micro-Architecture of the Intel Pentium
®
4 Processor
Page 4
Table of Contents
ABOUT THIS DOCUMENT ................................................................................................................. 5
INTRODUCTION ................................................................................................................................ 6
SIMD TECHNOLOGY AND STREAMING SIMD EXTENSIONS 2 ......................................................... 6
Summary of SIMD Technologies .............................................................................................................................................. 7
INTEL
®
NETBURST™ MICRO-ARCHITECTURE................................................................................. 9
The Design Considerations of the Intel NetBurst Micro-architecture............................................................................ 9
Overview of the Intel NetBurst Micro-architecture Pipeline ..........................................................................................10
The Front End .............................................................................................................................................................................10
The Out-of-order Core...............................................................................................................................................................11
Retirement ...................................................................................................................................................................................11
Front End Pipeline Detail..........................................................................................................................................................11
Prefetching...................................................................................................................................................................................12
Decoder........................................................................................................................................................................................12
Execution Trace Cache..............................................................................................................................................................12
Branch Prediction.......................................................................................................................................................................12
Branch Hints ...............................................................................................................................................................................13
Execution Core Detail ................................................................................................................................................................13
Instruction Latency and Throughput ......................................................................................................................................13
Execution Units and Issue Ports ..............................................................................................................................................14
Caches ..........................................................................................................................................................................................15
Data Prefetch...............................................................................................................................................................................15
Loads and Stores ........................................................................................................................................................................16
Store Forwarding........................................................................................................................................................................17
