Intel M20MYP1UR, Integration And Service Manual

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Intel® Server System M20MYP1UR System Integration and Service Guide
77
BIOS POST Progress Codes
Table 6 provides a list of all POST progress codes.
Table 6. POST progress codes
Post Code
(Hex) Nibble
LED 3
(MSB)
LED 2 LED 1
LED 0
(LSB) Description
SEC Phase
01
Upper 0 0 0 0
First POST code after CPU reset
Lower 0 0 0 1
02
Upper 0 0 0 0
Microcode load begin
Lower 0 0 1 0
03
Upper 0 0 0 0
CRAM initialization begin
Lower 0 0 1 1
04
Upper 0 0 0 0
PEI cache when disabled
Lower 0 1 0 0
05
Upper 0 0 0 0
SEC core at power on begin
Lower 0 1 0 1
06
Upper 0 0 0 0
Early CPU initialization during SEC phase.
Lower 0 1 1 0
Intel® Ultra Path Interconnect (Intel® UPI) RC (Fully leverage without platform change)
A1
Upper 1 0 1 0
Collect info such as SBSP, boot mode, reset type, etc.
Lower 0 0 0 1
A3
Upper 1 0 1 0
Setup minimum path between SBSP and other sockets
Lower 0 0 1 1
A7
Upper 1 0 1 0
Topology discovery and route calculation
Lower 0 1 1 1
A8
Upper 1 0 1 0
Program final route
Lower 1 0 0 0
A9
Upper 1 0 1 0
Program final IO SAD setting
Lower 1 0 0 1
AA
Upper 1 0 1 0
Protocol layer and other uncore settings
Lower 1 0 1 0
AB
Upper 1 0 1 0
Transition links to full speed operation
Lower 1 0 1 1