Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—Exponentiation
Acceleration Unit
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
914
Order Number: 306262-004US
25.3
Block Diagram
25.3.1
Operand Restrictions
Since the EAU implements modular arithmetic functions using a fixed-size datapath
ALU, there are some assumptions / restrictions for the operands that must be
observed. See
for details.
Figure 206. Exponentiation Acceleration Unit: Block Diagram
B4220-001
Address
Decode
2KB 3-ported RAM
ALU, Shifters, Accumulator,
multiplier, muxes, etc.
Calc
Block
Control
EAU
Sequencer
Block
EAU I/F
Control
Control &
Status
Registers,
Muxes
Control
Lines
Address
In
Range
Selects
Data
In
Data
Out
10
2
16
16
EAU Calc Book
EAU Register Interface
32
32
32
Table 287.
EAU Operand Size Restrictions and Assumptions
Operation
Operand Assumptions
Result (R)
Size
Addition
R = A + B
A, B must be same size (k bits)
A, B can be padded with leading zeros out to k bits
k+1 bits
Subtraction
R = A - B
A, B must be same size (k bits)
A, B can be padded with leading zeros out to k bits
k bits
Multiplication
R = A * B
A, B must be same size (k bits)
A, B can be padded with leading zeros out to k bits
2k bits
Modular Reduction
R = A mod N
size of A = 2k bits, size of N = k bits
MSB of N = 1, LSB of N can be 0 or 1
Note:
A can be padded with leading zeros.
k bits
Modular Exponentiation
R = M
e
mod N
M, e, N must be same size (k bits)
Modulus N is a k-bit number, i.e., 2
k-1
< n < 2
k
MSB & LSB of N = 1
Value of M < N
Note:
e can be padded with leading zeros.
k bits
Modular Inverse
R=A
-1
mod N
A, N must be same size (k bits)
Value of A < N
k bits
Note:
k = size of modulus in bits
