Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—Memory Controller
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
594
Order Number: 306262-004US
Since the MCU supports DDRI SDRAM bursting, the MCU increments the column
address based on the burst length of four for each DDRI SDRAM read or write burst.
The MCU supports a sequential and random burst types. Sequential bursting means
that the address issued to the DDRI SDRAM is incremented by the DDRI SDRAM device
in a linear fashion during the burst cycle. Random bursting means that the address
issued to the DDRI SDRAM is any address in a currently active page.
11.2.2.5
32-Bit Data Bus Width
The MCU supports a 32-bit data bus width and a minimum memory size of 32 Mbytes,
the maximum bus throughput is 1066 Mbytes/sec.
DDRI SDRAM address translation differs between 64- and 32-bit data bus widths. To
generate a 32-bit address to the memory subsystem, the internal address ADDR[31:2]
is shifted to the left by one bit prior to the address translations illustrated in
. This provides the granularity required for a 32-bit wide memory.
See
for an example of how shifting the address before generating the DDRI
SDRAM address on DDRI_MA[13:0] results in 32-bit addressing.
Table 210.
DDRI SDRAM Address Translation for 1 Gbitx16 Devices
DDRI_MA
[13:0]
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Row
I_A
D
[26]
I_A
D
[25]
I_A
D
[23]
I_A
D
[22]
I_A
D
[2
1]
I_A
D
[2
0]
I_A
D
[1
9]
I_A
D
[1
8]
I_A
D
[1
7]
I_A
D
[1
6]
I_A
D
[1
5]
I_A
D
[1
4]
I_A
D
[1
3]
I_A
D
[1
2]
Column
-
-
I_
A
D
[2
6
]
V
1
I_
A
D
[2
4
]
I_
A
D
[1
1
]
I_
A
D
[1
0
]
I_A
D
[9
]
I_A
D
[8
]
I_A
D
[7
]
I_A
D
[6
]
I_A
D
[5
]
I_A
D
[4
]
I_A
D
[3
]
Notes:
1.
A10 is used for precharge variations on the read or write command. See
for more details.
2.
For the Leaf Selects, see
.
3.
1 Gbitx16 addressing requires that ADDR[26] be presented as bit 13 of the row address instead of ADDR[27] as in
Figure 103. 64-Bit to 32-Bit Addressing
B4208-001
Data 0
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 9
Data 8
Data 7
Data 0
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 9
Data 8
Data 7
00H
08H
10H
18H
20H
00H
04H
08H
0CH
10H
14H
18H
1CH
20H
24H
Addr ess for
Address for
9
8
7
6
5
4
3
2
1
0
SDRAM Column
Address on MA[12:0]
64-bit Data
32-bi t Data
Example assumes that the 32-
bit address in question has t he
same row address independent
of memory bus width.
