Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 973 / 1898

3:74 Volume 3: Instruction Reference
fetchadd
fetchadd — Fetch and Add Immediate
Format: (
qp
) fetchadd4.
sem
.
ldhint r
1
= [
r
3
],
inc
3
four_byte_form M17
(
qp
) fetchadd8.
sem
.
ldhint r
1
= [
r
3
],
inc
3
eight_byte_form M17
Description:
A value consisting of four or eight bytes is read from memory starting at the address
specified by the value in GR
r
3
. The value is zero extended and added to the
sign-extended immediate value specified by
inc
3
. The values that may be specified by
inc
3
are: -16, -8, -4, -1, 1, 4, 8, 16. The least significant four or eight bytes of the sum
are then written to memory starting at the address specified by the value in GR
r
3
. The
zero-extended value read from memory is placed in GR
r
1
and the NaT bit
corresponding to GR
r
1
is cleared.
The
sem
completer specifies the type of semaphore operation. These operations are
described in Table 2-28 . See Section 4.4.7, “Sequentiality Attribute and Ordering” on
page 2:82 for details on memory ordering.
The memory read and write are guaranteed to be atomic for accesses to pages with
cacheable, writeback memory attribute. For accesses to other memory types, atomicity
is platform dependent. Details on memory attributes are described in
Section 4.4,
“Memory Attributes” on page 2:75 .
If the address specified by the value in GR
r
3
is not naturally aligned to the size of the
value being accessed in memory, an Unaligned Data Reference fault is taken
independent of the state of the User Mask alignment checking bit, UM.ac (PSR.ac in the
Processor Status Register).
Both read and write access privileges for the referenced page are required. The write
access privilege check is performed whether or not the memory write is performed.
Only accesses to UCE pages or cacheable pages with write-back write policy are
permitted. Accesses to NaTPages result in a Data NaT Page Consumption fault.
Accesses to pages with other memory attributes cause an Unsupported Data Reference
fault.
On a processor model that supports exported
fetchadd
, a
fetchadd
to a UCE page
causes the fetch-and-add operation to be exported outside of the processor; if the
platform does not support exported
fetchadd
, the operation is undefined. On a
processor model that does not support exported
fetchadd
, a
fetchadd
to a UCE page
causes an Unsupported Data Reference fault. See Section 4.4.9, “Effects of Memory
Attributes on Memory Reference Instructions” on page 2:86 .
The value of the
ldhint
completer specifies the locality of the memory access. The values
of the
ldhint
completer are given in Table 2-34 on page 3:152 . Locality hints do not
affect program functionality and may be ignored by the implementation. See
Section 4.4.6, “Memory Hierarchy Control and Consistency” on page 1:69 for details.
Table 2-28. Fetch and Add Semaphore Types
sem
Completer
Ordering
Semantics
Semaphore Operation
acq Acquire The memory read/write is made visible prior to all subsequent data memory
accesses.
rel Release The memory read/write is made visible after all previous data memory
accesses.