Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 73 / 1898

1:62 Volume 1, Part 1: Application Programming Model
For these instructions, if any source contains a deferred exception token, all predicate
targets are either cleared or left unchanged, depending on the compare type (see
Table 4-10 on page 1:56 ). Software can use this behavior to ensure that any dependent
conditional branches are not taken and any dependent predicated instructions are
nullified. See
“Predication” on page 1:54 .
Deferred exception tokens can also be tested for with certain compare instructions. The
test NaT (
tnat
) instruction tests the NaT bit corresponding to the specified general
register and writes two predicate results. The floating-point class (
fclass
) instruction
can be used to test for a NaTVal in a floating-point register and write the result to two
predicate registers.
fclass
does not clear both predicate targets in the presence of a
NaTVal input if NaTVal is one of the classes being tested for.
4.4.4.4 Control Speculation without Recovery
A non-speculative instruction that reads a register containing a deferred exception
token will raise a Register NaT Consumption fault. Such instructions can be thought of
as performing a non-recoverable speculation check operation. In some compilation
environments, it may be true that the only exceptions that are deferred are fatal errors.
In such a program, if the result of a speculative calculation is checked and a deferred
exception token is found, execution of the program is terminated. For such a program,
the results of speculative calculations can be checked simply by using non-speculative
instructions.
4.4.4.5 Operating System Control over Exception Deferral
An additional mechanism is defined that allows the operating system to control the
exception behavior of speculative loads. The operating system has the option to select
which exceptions are deferred automatically in hardware and which exceptions will be
handled (and possibly deferred) by software. See
Section 5.5.5, “Deferral of
Speculative Load Faults” on page 2:105 .
4.4.4.6 Register Spill and Fill
Special store and load instructions are provided for spilling a register to memory and
preserving any deferred exception token, and for restoring a spilled register.
The spill and fill general register instructions (
st8.spill
,
ld8.fill
) are defined to
save/restore a general register along with the corresponding NaT bit.
The
st8.spill
instruction writes a general register’s NaT bit into the User NaT
Collection application register (UNAT), and, if the NaT bit was 0, writes the register’s
64-bit data portion to memory. If the register’s NaT bit was 1, the UNAT is updated, but
the memory update is implementation specific. As stated in
Section 4.4.4.1, “Control
Speculation Concepts” , software cannot rely on the 64-bit data portion spilled to
memory for a NaT'ed GR. Although guidance is given here for processor
implementations, other allowed implementation strategies may be added in the future,
and software should not rely on the implementation guidance.
Processor implementations (hardware and firmware) must consistently follow one of
two spill behaviors (but software should not count on implementations being limited to
these behaviors):