Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 448 / 1898

2:200 Volume 2, Part 1: Interruption Vector Descriptions
Name
Debug vector (0x5900)
Cause A debug fault has occurred. Either the instruction address matches the parameters set
up in the instruction debug registers, or the data address of a load, store, semaphore,
or mandatory RSE fill or spill matches the parameters set up in the data debug
registers. All IA-32 instruction set debug events are delivered on the
IA_32_Exception(Debug) vector; see
Chapter 9, “IA-32 Interruption Vector
Descriptions.” IA-32 instructions can not raise this fault, IA-32 debug events are
delivered on the IA_32_Exception(Debug) vector.
Interruptions on this vector:
IR Data Debug fault
Instruction Debug fault
Data Debug fault
Parameters IIP, IPSR, IIPA, IFS – are defined; refer to page 2:165 for a detailed description.
IIB0, IIB1 – If implemented, for Data Debug faults, the IIB registers contain the
instruction bundle pointed to by IIP. The IIB registers are undefined for IR Data Debug
and Instruction Debug faults. Please refer to
Section 3.3.5.10, “Interruption Instruction
Bundle Registers (IIB0-1 – CR26, 27)” on page 2:42 for details on the IIB registers.
If the fault is due to a data debug fault or an IR Data Debug fault:
• IFA – The address of the data being referenced.
• ISR – The value for the ISR bits depend on the type of access performed and are
specified below. For mandatory RSE fill or spill references, ISR.ed is always 0.
If the fault is due to an instruction debug fault:
• IFA – Faulting instruction fetch address.
• ISR – The ISR.ei bits are set to indicate which instruction caused the exception. The
defined ISR bits are specified below.
Notes On an instruction reference this fault is suppressed if the PSR.db bit is 0 or if the PSR.id
bit is 1. On a data reference this fault is suppressed if the PSR.db bit is 0 or if the
PSR.dd bit is 1. The only non-access data operations which can cause a debug fault are
the
probe.fault
and
lfetch.fault
instructions.
If unaligned accesses are being performed with debug faults enabled, this fault may be
taken even though there is not a match for the address programmed in the breakpoint
register. See
Section 7.1.2, “Debug Address Breakpoint Match Conditions” on
page 2:154 .
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 code{3:0}
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
0 ed ei 0 ni ir rs sp na r w 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
0 0 ei 0 ni 0 0 0 0 0 0 1