Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 280 / 1898

2:32 Volume 2, Part 1: System State and Programming Model
For the DCR exception deferral bits, when the bit is 1, and a speculative load results in
the specified fault condition, and the speculative load’s code page exception deferral bit
(ITLB.ed) is 1, the exception is deferred by setting the speculative load target register
to NaT or NaTVal. Otherwise, the specified fault is taken on the speculative load. For a
description of faults on speculative loads see
“Deferral of Speculative Load Faults” on
page 2:105 .
Since DCR.be also controls byte ordering of VHPT references that are the result of
instruction misses, DCR.be requires instruction serialization. Other DCR bits require
data serialization only.
3.3.4.2 Interval Time Counter and Match Register (ITC – AR44 and ITM – CR1)
The Interval Time Counter (ITC) and Interval Timer Match (ITM) register support
elapsed time notification, see
Figure 3-4 and Figure 3-5 .
The ITC is a free-running 64-bit counter that counts up at a fixed relationship to the
input clock to the processor. The ITC may be clocked at a somewhat lower frequency
than the instruction execution frequency. This clocking relationship is described in the
PAL procedure PAL_FREQ_RATIOS on page
2:393 . The ITC is guaranteed to be clocked
at a constant rate, even if the instruction execution frequency may vary. The ITC
counting rate is not affected by power management mechanisms.
dk 10 Defer Key Miss faults only – When 1, and a Key Miss fault is deferred,
lower priority Access Bit, Access Rights or Debug faults may still be
delivered. A Key Miss fault, deferred or not, precludes concurrent Key
Permission faults. This bit is ignored by IA-32 instructions. data
dx 11 Defer Key Permission faults only – When 1, and a Key Permission fault is
deferred, lower priority Access Bit, Access Rights or Debug faults may
still be delivered. This bit is ignored by IA-32 instructions. data
dr 12 Defer Access Rights faults only – When 1, and an Access Rights fault is
deferred, lower priority Access Bit or Debug faults may still be delivered.
This bit is ignored by IA-32 instructions. data
da 13 Defer Access Bit faults only – When 1, and an Access Bit fault is
deferred, lower priority Debug faults may still be delivered. This bit is
ignored by IA-32 instructions. data
dd 14 Defer Debug faults – When 1, Data Debug faults on speculative loads are
deferred. This bit is ignored by IA-32 instructions. data
rv 7:3,
63:15 reserved reserved
Figure 3-4. Interval Time Counter (ITC – AR44)
63 0
ITC
64
Figure 3-5. Interval Timer Match Register (ITM – CR1)
63 0
ITM
64
Table 3-5. Default Control Register Fields (Continued)
Field Bit Description
Serialization
Required