Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1766 / 1898

4:464 Volume 4: IA-32 SSE Instruction Reference
4.3 Single Instruction Multiple Data
The Intel SSE architecture uses the Single Instruction Multiple Data (SIMD) technique.
This technique speeds up software performance by processing multiple data elements
in parallel, using a single instruction. The Intel SSE architecture supports operations on
packed single-precision floating-point data types, and the additional SIMD Integer
instructions support operations on packed quadrate data types (byte, word, or
double-word). This approach was chosen because most 3D graphics and DSP
applications have the following characteristics:
• Inherently parallel
• Wide dynamic range, hence floating-point based
• Regular and re-occurring memory access patterns
• Localized re-occurring operations performed on the data
• Data independent control flow
The Intel SSE architecture is 100% compatible with the IEEE Standard 754 for Binary
Floating-point Arithmetic. The SSE instructions are accessible from all IA execution
modes: Protected mode, Real address mode, and Virtual 8086 mode.New Features
The Intel SSE architecture provides the following new features, while maintaining
backward compatibility with all existing Intel architecture microprocessors, IA
applications and operating systems.
• New data type
• Eight SSE registers
• Enhanced instruction set
The Intel SSE architecture can enhance the performance of applications that use these
features.
4.4 New Data Types
The principal data type of the Intel SSE architecture is a packed single-precision
floating-point operand, specifically:
• Four 32-bit single-precision (SP) floating-point numbers ( Figure 4-1 ).
The SIMD Integer instructions will operate on the packed byte, word or doubleword
data types. The prefetch instruction works on typeless data of size 32 bytes or greater.
Figure 4-1. Packed Single-FP Data Type
Packed Single-FP
127 96 95 65 63 32 31 0