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Volume 4: IA-32 Intel
®
MMX™ Technology Instruction Reference
4:401
MOVD—Move 32 Bits
Description
Copies doubleword from the source operand (second operand) to the destination
operand (first operand). Source and destination operands can be MMX technology
registers, memory locations, or 32-bit general-purpose registers; however, data cannot
be transferred from an MMX technology register to an MMX technology register, from
one memory location to another memory location, or from one general-purpose register
to another general-purpose register.
When the destination operand is an MMX technology register, the 32-bit source value is
written to the low-order 32 bits of the 64-bit MMX technology register and
zero-extended to 64 bits (see
). When the source operand is an MMX
technology register, the low-order 32 bits of the MMX technology register are written to
the 32-bit general-purpose register or 32-bit memory location selected with the
destination operand.
Operation
IF DEST is MMX register
THEN
DEST
ZeroExtend(SRC);
ELSE (* SRC is MMX register *)
DEST
LowOrderDoubleword(SRC);
Opcode
Instruction
Description
0F 6E /r
MOVD
mm, r/m32
Move doubleword from
r/m32
to
mm
.
0F 7E /r
MOVD
r/m32, mm
Move doubleword from
mm
to
r/m32
.
Figure 3-1.
Operation of the MOVD Instruction
3006010
MOVD m32, mm
MOVD mm, r32
63
31
0
32 31
mm
m32
15
0
0
00000000
b b
b b r32
b b b b
63
mm
0
xxxxxxxx
b b b
b
b
b
b
W
W
32 31
3
2
1
0
3
0
1
2
N+1
N+1
3
2
1
0
b
3
2
1
0
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...