Volume 3: Resource and Dependency Semantics
3:371
Resource and Dependency Semantics
5
5.1
Reading and Writing Resources
An Itanium instruction is said to be a
reader
of a resource if the instruction’s qualifying
predicate is 1 or it has no qualifying predicate or is one of the instructions that reads a
resource even when its qualifying predicate is 0, and the execution of the instruction
depends on that resource.
An Itanium instruction is said to be an
writer
of a resource if the instruction’s
qualifying predicate is 1 or it has no qualifying predicate or writes the resource even
when the qualifying predicate is 0, and the execution of the instruction writes that
resource.
An Itanium instruction is said to be a reader or writer of a resource even if it only
sometimes depends on that resource and it cannot be determined statically whether
the resource will be read or written. For example,
cover
only writes CR[IFS] when
PSR.ic is 0, but for purposes of dependency, it is treated as if it always writes the
resource since this condition cannot be determined statically. On the other hand,
rsm
conditionally writes several bits in the PSR depending on a mask which is encoded as an
immediate in the instruction. Since the PSR bits to be written can be determined by
examining the encoded instruction, the instruction is treated as only writing those bits
which have a corresponding mask bit set. All exceptions to these general rules are
described in this appendix.
5.2
Dependencies and Serialization
A
RAW
(Read-After-Write) dependency is a sequence of two events where the first is a
writer of a resource and the second is a reader of the same resource. Events may be
instructions, interruptions, or other ‘uses’ of the resource such as instruction stream
fetches and VHPT walks.
covers only dependencies based on instruction
readers and writers.
A
WAW
(Write-After-Write) dependency is a sequence of two events where both events
write the resource in question. Events may be instructions, interruptions, or other
‘updates’ of the resource.
covers only dependencies based on instruction
writers.
A
WAR
(Write-After-Read) dependency is a sequence of two instructions, where the
first is a reader of a resource and the second is a writer of the same resource. Such
dependencies are always allowed except as indicated in
related to instruction readers and writers are included.
A
RAR
(Read-After-Read) dependency is a sequence of two instructions where both are
readers of the same resource. Such dependencies are always allowed.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...