Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1250 / 1898

Volume 3: Instruction Formats 3:351
The indirect branch instructions encoded within major opcodes 0 use a 3-bit opcode
extension field in bits 8:6 (btype) to distinguish the branch types as shown in
Table 4-49 .
The indirect return branch instructions encoded within major opcodes 0 use a 3-bit
opcode extension field in bits 8:6 (btype) to distinguish the branch types as shown in
Table 4-50 .
All of the branch instructions have a 1-bit sequential prefetch opcode hint extension
field, p, in bit 12.
Table 4-51 summarizes these assignments.
The IP-relative and indirect branch instructions all have a 2-bit branch prediction
“whether” opcode hint extension field in bits 34:33 (wh) as shown in
Table 4-52 .
Indirect call instructions have a 3-bit “whether” opcode hint extension field in bits
34:32 (wh) as shown in
Table 4-53 .
Table 4-49. Indirect Branch Types
Opcode
Bits 40:37
x
6
Bits 32:27
btype
Bits 8:6
0 20
0 br.cond B4
1 br.ia B4
2
e
3
e
4
e
5
e
6
e
7
e
Table 4-50. Indirect Return Branch Types
Opcode
Bits 40:37
x
6
Bits 32:27
btype
Bits 8:6
0 21
0
e
1
e
2
e
3
e
4 br.ret B4
5
e
6
e
7
e
Table 4-51. Sequential Prefetch Hint Completer
p
Bit 12
ph
0 .few
1 .many