Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1113 / 1898

3:214 Volume 3: Instruction Reference
pmpyshr
pmpyshr — Parallel Multiply and Shift Right
Format: (
qp
) pmpyshr2
r
1
=
r
2
,
r
3
,
count
2
signed_form I1
(
qp
) pmpyshr2.u
r
1
=
r
2
,
r
3
,
count
2
unsigned_form I1
Description:
The four 16-bit data elements of GR
r
2
are multiplied by the corresponding four 16-bit
data elements of GR
r
3
as shown in Figure 2-37 . This multiplication can either be signed
(pmpyshr2), or unsigned (pmpyshr2.u). Each product is then shifted to the right
count
2
bits, and the least-significant 16-bits of each shifted product form 4 16-bit results,
which are placed in GR
r
1
. A
count
2
of 0 gives the 16 low bits of the results, a
count
2
of 16
gives the 16 high bits of the results. The allowed values for
count
2
are given in
Table 2-46 .
Table 2-46. Parallel Multiply and Shift Right Shift Options
count
2
Selected Bit Field from Each 32-bit Product
0 15:0
7 22:7
15 30:15
16 31:16
Figure 2-37. Parallel Multiply and Shift Right Operation
GR r
2
:
GR r
1
:
GR r
3
:
* * * *
pmpyshr2
32-bit
Shift Right
count
2
Bits
Products
16-bit
Source
Elements
16-bit
Result
Elements