Intel Itanium 9150M, Manual

Page: 324 / 420

Volume 3: Instruction Formats 3:315
4.3.1.9 Bit Strings
I9
4.3.2 Integer Shifts
The integer shift, test bit, and test NaT instructions are encoded within major opcode 5
using a 2-bit opcode extension field in bits 35:34 (x
2
) and a 1-bit opcode extension
field in bit 33 (x). The extract and test bit instructions also have a 1-bit opcode
extension field in bit 13 (y).
Table 4-21 shows the test bit, extract, and shift right pair
assignments.
Most deposit instructions also have a 1-bit opcode extension field in bit 26 (y).
Table 4-22 shows these assignments.
4.3.2.1 Shift Right Pair
I10
40 37 36 35 34 33 32 31 30 29 28 27 26 20 19 13 12 6 5 0
7 z
a
x
2a
z
b
v
e
x
2c
x
2b
r
3
0 r
1
qp
4 1 2 1 1 2 2 1 7 7 7 6
Instruction Operands Opcode
Extension
z
a
z
b
v
e
x
2a
x
2b
x
2c
popcnt
r
1
= r
3
7 0 1 0 1 1
2
clz 3
Table 4-21. Integer Shift/Test Bit/Test NaT 2-bit Opcode Extensions
Opcode
Bits 40:37
x
2
Bits 35:34
x
Bit 33
y
Bit 13
0 1
5
0
0
Test Bit ( Table 4-23 ) Test NaT/Test Feature ( Table 4-23 )
1 extr.u I11 extr I11
2
3
shrp I10
Table 4-22. Deposit Opcode Extensions
Opcode
Bits 40:37
x
2
Bits 35:34
x
Bit 33
y
Bit 26
0 1
5
0
1
Test Bit/Test NaT/Test Feature ( Table 4-23 )
1 dep.z I12 dep.z – imm
8
I13
2
3
dep – imm
1
I14
40 37 36 35 34 33 32 27 26 20 19 13 12 6 5 0
5 x
2
x count
6d
r
3
r
2
r
1
qp
4 1 2 1 6 7 7 7 6
Instruction Operands Opcode
Extension
x
2
x
shrp r
1
= r
2
, r
3
, count
6
5 3 0