Intel Itanium 9150M, Manual

Page: 260 / 420

Volume 3: Instruction Reference 3:251
st
st — Store
Format: (
qp
) st
sz
.
sttype
.
sthint
[
r
3
] =
r
2
normal_form, no_base_update_form M6
(
qp
) st
sz
.
sttype
.
sthint
[
r
3
] =
r
2
,
imm
9
normal_form, imm_base_update_form M5
(
qp
) st16.
sttype
.
sthint
[
r
3
] =
r
2
, ar.csd sixteen_byte_form, no_base_update_form M6
(
qp
) st8.spill.
sthint
[
r
3
] =
r
2
spill_form, no_base_update_form M6
(
qp
) st8.spill.
sthint
[
r
3
] =
r
2
,
imm
9
spill_form, imm_base_update_form M5
Description:
A value consisting of the least significant
sz
bytes of the value in GR
r
2
is written to
memory starting at the address specified by the value in GR
r
3
. The values of the
sz
completer are given in Table 2-32 on page 3:151 . The
sttype
completer specifies special
store operations, which are described in Table 2-50 . If the NaT bit corresponding to GR
r
3
is 1, or in sixteen_byte_form or normal_form, if the NaT bit corresponding to GR
r
2
is
1, a Register NaT Consumption fault is taken.
In the sixteen_byte_form, two 8-byte values are stored as a single, 16-byte atomic
memory write. The value in GR
r
2
is written to memory starting at the address specified
by the value in GR
r
3
. The value in the Compare and Store Data application register
(AR[CSD]) is written to memory starting at the address specified by the value in GR
r
3
plus 8.
In the spill_form, an 8-byte value is stored, and the NaT bit corresponding to GR
r
2
is
copied to a bit in the UNAT application register. This instruction is used for spilling a
register/NaT pair. See
Section 4.4.4, “Control Speculation” on page 1:60 for details.
In the imm_base_update form, the value in GR
r
3
is added to a signed immediate value
(
imm
9
) and the result is placed back in GR
r
3
. This base register update is done after the
store, and does not affect the store address, nor the value stored (for the case where
r
2
and
r
3
specify the same register). Base register update is not supported for the
st16
instruction.
For more details on ordered stores see Section 4.4.7, “Memory Access Ordering” on
page 1:73 .
The ALAT is queried using the physical memory address and the access size, and all
overlapping entries are invalidated.
The value of the
sthint
completer specifies the locality of the memory access. The values
of the
sthint
completer are given in Table 2-51 . A prefetch hint is implied in the base
update forms. The address specified by the value in GR
r
3
after the base update acts as
a hint to prefetch the indicated cache line. This prefetch uses the locality hints specified
by
sthint
. See Section 4.4.6, “Memory Hierarchy Control and Consistency” on
page 1:69 .
Hardware support for
st16
instructions that reference a page that is neither a
cacheable page with write-back policy nor a NaTPage is optional. On processor models
that do not support such
st16
accesses, an Unsupported Data Reference fault is raised
when an unsupported reference is attempted.
Table 2-50. Store Types
sttype
Completer
Interpretation Special Store Operation
none Normal store
rel Ordered store An ordered store is performed with release semantics.