Intel Itanium 2 Processor Datasheet Download Page 63

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Datasheet

Pinout Specifications

GND

V15

A038#

AA38#/AB38#

V16

IN/OUT

GND

V17

A029#

AA29#/xTPRValue2#

V18

IN/OUT

GND

V19

A045#

AA45#/AB45#

V20

IN/OUT

GND

V21

A047#

AA47#/AB47#

V22

IN/OUT

GND

V23

A040#

AA40#/AB40#

V24

IN/OUT

GND

V25

GND

W02

A006#

AA06#/EXF3#

W03

IN/OUT

A012#

AA12#/BE4#

W05

IN/OUT

A014#

AA14#/BE6#

W07

IN/OUT

A021#

AA21#/DID5#

W09

IN/OUT

A026#

AA26#/AB26#

W11

IN/OUT

A022#

AA22#/DID6#

W13

IN/OUT

A037#

AA37#/AB37#

W15

IN/OUT

A032#

AA32#/ATTR0#

W17

IN/OUT

A030#

AA30#/xTPRValue3#

W19

IN/OUT

A044#

AA44#/AB44#

W21

IN/OUT

A046#

AA46#/AB46#

W23

IN/OUT

A041#

AA41#/AB41#

W25

IN/OUT

GND

Y01

A007#

AA07#/EXF4#

Y02

IN/OUT

GND

Y03

A013#

AA13#/BE5#

Y04

IN/OUT

GND

Y05

A008#

AA08#/BE0#

Y06

IN/OUT

GND

Y07

A017#

AA17#/DID1#

Y08

IN/OUT

GND

Y09

A024#

AA24#/DID8#

Y10

IN/OUT

GND

Y11

A025#

AA25#/DID9#

Y12

IN/OUT

GND

Y13

A034#

AA34#/ATTR2#

Y14

IN/OUT

GND

Y15

A036#

AA36#/AB36#

Y16

IN/OUT

GND

Y17

Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 11 of 15)

Pin Name

System Bus

Signal Name

Pin

Location

Input/Output

Notes

Summary of Contents for Itanium 2 Processor

Page 1: ...ocessor 1 6 GHz with 6 MB L3 Cache Intel Itanium 2 Processor 1 5 GHz with 6 MB L3 Cache Intel Itanium 2 Processor 1 5 GHz with 4 MB L3 Cache Intel Itanium 2 Processor 1 4 GHz with 4 MB L3 Cache Intel...

Page 2: ...atsoever for conflicts or incompatibilities arising from future changes to them The Intel Itanium 2 processor may contain design defects or errors known as errata which may cause the product to deviat...

Page 3: ...ulse Duration 24 2 5 3 Activity Factor 24 2 5 4 Reading Overshoot Undershoot Specification Tables 25 2 5 5 Determining if a System Meets the Overshoot Undershoot Specifications 25 2 5 6 Wired OR Signa...

Page 4: ...91 A 1 1 A 49 3 I O 91 A 1 2 A20M I 91 A 1 3 ADS I O 91 A 1 4 AP 1 0 I O 91 A 1 5 ASZ 1 0 I O 91 A 1 6 ATTR 3 0 I O 92 A 1 7 BCLKp BCLKn I 92 A 1 8 BE 7 0 I O 92 A 1 9 BERR I O 93 A 1 10 BINIT I O 94...

Page 5: ...TMS I 105 A 1 66 TND I O 105 A 1 67 TRDY I 105 A 1 68 TRST I 105 A 1 69 WSNP I O 105 A 2 Signal Summaries 105 Figures 2 1 Generic Clock Waveform 22 2 2 SMSC Clock Waveform 22 2 3 System Bus Signal Wav...

Page 6: ...s 27 2 16 Itanium 2 9 MB Processors Source Synchronous AGTL Signal Group Time Dependent Overshoot Undershoot Tolerance for 533 MHz System Bus 27 2 17 Itanium 2 Processors 1 66 GHz Source Synchronous A...

Page 7: ...89 6 15 Thermal Sensing Device Configuration Register 89 6 16 Thermal Sensing Device Conversion Rate Register 90 A 1 Address Space Size 92 A 2 Effective Memory Type Signal Encoding 92 A 3 Special Tran...

Page 8: ...MB and Itanium 2 processor 1 3 GHz 3 MB June 2003 003 Updated content to include information pertaining to Itanium 2 processor 1 5 GHz 4 MB and Itanium 2 processor 1 6 GHz 6 MB and 9 MB November 2004...

Page 9: ...technical computing applications SMBus compatibility and comprehensive reliability availability and serviceability RAS features make the Itanium 2 processor ideal for applications requiring high up t...

Page 10: ...10 Datasheet...

Page 11: ...he hardware employs dynamic prefetch branch prediction a register scoreboard and non blocking caches to optimize for compile time non determinism Three levels of on die cache minimize overall memory l...

Page 12: ...tive low signal This means that a signal is in the active state based on the name of the signal when driven to a low level For example when RESET is low a processor reset has been requested When NMI i...

Page 13: ...te 251141 Intel Itanium Architecture Software Developer s Manual Volume 1 Application Architecture 245317 Intel Itanium Architecture Software Developer s Manual Volume 2 System Architecture 245318 Int...

Page 14: ...14 Datasheet Introduction...

Page 15: ...inputs use differential receivers which require a reference signal VREF VREF is used by the receivers to determine if a signal is a logical 0 or a logical 1 The Itanium 2 processor generates VREF on d...

Page 16: ...s signals and LVTTL power pod signals are driven using the 3 3 V CMOS logic levels listed in Table 2 8 and Table 2 9 respectively 2 2 2 Signal Descriptions Appendix A Signals Reference contains functi...

Page 17: ...re terminated as indicated above VCCMON VSSMON These pins provide a remote sense connection from the processor to the power pod No connections that constitute a current load can be made to these pins...

Page 18: ...gn power is an estimate of the power dissipation for the Itanium 2 processor offering while executing a worst case application mix under nominal VCC PS and worst case temperature Table 2 3 Itanium 2 P...

Page 19: ...nd processor parasitics if applicable Capacitance values guaranteed by design for all AGTL buffers Table 2 5 Power Good Signal DC Specifications Symbol Parameter Minimum Maximum Unit Notes VIL Input L...

Page 20: ...lue specified for IOL2 applies only to THRMALERT which is an open drain signal ILI Input Leakage Current 10 A ILO Output Leakage Current 10 A Table 2 9 LVTTL Signal DC Specifications Symbol Parameter...

Page 21: ...ned as peak to peak variation measured over 10000 cycles peak to peak jitter 4 Measured on cross point of rising edge of BCLKp and falling edge of BCLKn 5 The system clock skew is 60 ps 6 VPPmin is de...

Page 22: ...atic voltages or electric fields Figure 2 1 Generic Clock Waveform 000615 Figure 2 2 SMSC Clock Waveform 000618 80 Trise Trise Rise Time Tfall Fall Time High Time Thigh Low Time Tlow 20 Tfall Thigh Tl...

Page 23: ...able 2 21 These specifications must not be violated at any time regardless of bus activity or system state Within these specifications are threshold levels that define different allowed pulse duration...

Page 24: ...200 clock cycles For source synchronous signals data and associated strobes the activity factor is in reference to the strobe edge The highest frequency of assertion of any source synchronous signal...

Page 25: ...l being measured If the pulse duration measured is less than the pulse duration shown in the table then the signal meets the specifications 6 Undershoot events must be analyzed separately from oversho...

Page 26: ...Undershoot Tolerance Parameter Description Specification Units VCTERM I O power supply voltage nominal 1 20 V VMAX Maximum absolute voltage for system bus signals at the input of the receiver buffers...

Page 27: ...2 2351 2 5 2 5 2 5 2 5 2 5 1 5 0 3 2 5 2 5 2 5 2 5 2 5 2 5 2 5 1 45 0 25 2 5 2 5 2 5 2 5 2 5 2 5 2 5 Table 2 16 Itanium 2 9 MB Processors Source Synchronous AGTL Signal Group Time Dependent Overshoot...

Page 28: ...0423 0 0858 0 4297 1 75 0 55 0 0129 0 0172 0 0258 0 0517 0 1292 0 2585 1 2953 1 7 0 5 0 0387 0 0516 0 0775 0 1553 0 3882 0 7748 1 5 1 65 0 45 0 1158 0 1544 0 2311 0 4629 1 1564 1 5 1 5 1 6 0 4 0 3429...

Page 29: ...ute Maximum V Pulse Duration ns Over shoot Under shoot AF 11 NOTES 1 Activity Factor 1 means signal toggles every 7 5 ns AF 0 75 AF 0 5 AF 0 25 AF 0 1 AF 0 05 AF 0 01 1 8 0 6 0 0385 0 0513 0 0770 0 15...

Page 30: ...VSS Processor connection is provided on the power tab connector as well 1 6 0 4 2 4567 3 3 3 3 3 3 1 55 0 35 3 3 3 3 3 3 3 1 5 0 3 3 3 3 3 3 3 3 NOTES 1 Activity Factor 1 means signal toggles every 6...

Page 31: ...shown in Table 2 24 and in Figure 2 5 Full power to the processor is defined in Table 2 2 Table 2 23 Processor Core Voltage Identification Code1 NOTES 1 Nominal settings require regulation to 7 at VC...

Page 32: ...anium 2 Processor Hardware Developer s Manual for complete information on Itanium 2 processor system bus clock and processor clocking Table 2 24 Processor Power States State Transition Ramp Rate Comme...

Page 33: ...uence as defined below Cold Reset Sequence The bus ratio configuration pins A 21 17 must be asserted the entire time RESET is asserted RESET must be asserted before PWRGOOD is asserted The duration fr...

Page 34: ...p signal Configuration signals other than A 21 17 must be asserted four BCLKs prior to the deasserted edge of RESET and must remain valid for two BCLKs minimum to three BCLKs maximum after the deasser...

Page 35: ...ESET Bus Ratio A 21 17 TA 1 15 ns minimum set up time to BCLK for deassertion edge of RESET TB 1 ms minimum for warm reset TD 2 BCLKs minimum 3 BCLKs maximum TE 4 BCLKs minimum TF 2 BCLKs minimum 3 BC...

Page 36: ...ust be used CPUPRES Must be used Reserved Pins N C N C NOTES 1 L GND H VCTERM 2 AGTL output signals SBSY 0 1 DBSY 0 1 and DRDY 0 1 may be left as N C if not used on platform 3 Should be properly termi...

Page 37: ...A 31 V C TER M D 94 D 59 D 87 V C TER M D 84 N C V C TER M D 75 D 68 V C TER M D 65 G N D N C V C TER M G N D G N D TN D G N D B IN IT G N D G N D A 28 G N D D 92 G N D D 91 G N D D 81 G N D D 78 G N...

Page 38: ...OUT A012 AA12 BE4 W05 IN OUT A013 AA13 BE5 Y04 IN OUT A014 AA14 BE6 W07 IN OUT A015 AA15 BE7 V08 IN OUT A016 AA16 DID0 U13 IN OUT A017 AA17 DID1 Y08 IN OUT A018 AA18 DID2 U09 IN OUT A019 AA19 DID3 V1...

Page 39: ...IT BINIT AA15 IN OUT BNR BNR U17 IN OUT BPM0 BPM0 AD22 IN OUT BPM1 BPM1 AC25 IN OUT BPM2 BPM2 AE23 IN OUT BPM3 BPM3 AC23 IN OUT BPM4 BPM4 AD24 IN OUT BPM5 BPM5 AB24 IN OUT BPRI BPRI AE19 IN BR0 BREQ0...

Page 40: ...UT D028 D28 M06 IN OUT D029 D29 R05 IN OUT D030 D30 T02 IN OUT D031 D31 R07 IN OUT D032 D32 H10 IN OUT D033 D33 C11 IN OUT D034 D34 D10 IN OUT D035 D35 C09 IN OUT D036 D36 D12 IN OUT D037 D37 D08 IN O...

Page 41: ...UT D069 D69 F18 IN OUT D070 D70 C19 IN OUT D071 D71 G15 IN OUT D072 D72 G17 IN OUT D073 D73 C17 IN OUT D074 D74 E19 IN OUT D075 D75 H14 IN OUT D076 D76 H16 IN OUT D077 D77 H18 IN OUT D078 D78 J15 IN O...

Page 42: ...110 J25 IN OUT D111 D111 H20 IN OUT D112 D112 L21 IN OUT D113 D113 L25 IN OUT D114 D114 K22 IN OUT D115 D115 M24 IN OUT D116 D116 L23 IN OUT D117 D117 K20 IN OUT D118 D118 M20 IN OUT D119 D119 N25 IN...

Page 43: ...N OUT DRDY DRDY AC11 IN OUT DRDY0 DRDY_C1 AA07 OUT DRDY1 DRDY_C2 AA21 OUT FERR FERR AH25 OUT GND GND A01 IN GND GND A03 IN GND GND A05 IN GND GND A08 IN GND GND A13 IN GND GND A16 IN GND GND A19 IN GN...

Page 44: ...GND AD23 IN GND GND AD25 IN GND GND AE02 IN GND GND AE24 IN GND GND AF01 IN GND GND AF05 IN GND GND AF07 IN GND GND AF09 IN GND GND AF11 IN GND GND AF13 IN GND GND AF15 IN GND GND AF17 IN GND GND AF1...

Page 45: ...N GND GND C06 IN GND GND C10 IN GND GND C14 IN GND GND C18 IN GND GND C22 IN GND GND D01 IN GND GND D03 IN GND GND D05 IN GND GND D07 IN GND GND D09 IN GND GND D11 IN GND GND D13 IN GND GND D15 IN GND...

Page 46: ...GND GND H09 IN GND GND H11 IN GND GND H13 IN GND GND H15 IN GND GND H17 IN GND GND H19 IN GND GND H21 IN GND GND H23 IN GND GND H25 IN GND GND J01 IN GND GND J04 IN GND GND J08 IN GND GND J12 IN GND G...

Page 47: ...GND GND M25 IN GND GND N04 IN GND GND N20 IN GND GND N24 IN GND GND P01 IN GND GND P03 IN GND GND P05 IN GND GND P07 IN GND GND P09 IN GND GND P11 IN GND GND P13 IN GND GND P15 IN GND GND P17 IN GND G...

Page 48: ...IN GND GND V17 IN GND GND V19 IN GND GND V21 IN GND GND V23 IN GND GND V25 IN GND GND W02 IN GND GND Y01 IN GND GND Y03 IN GND GND Y05 IN GND GND Y07 IN GND GND Y09 IN GND GND Y11 IN GND GND Y13 IN G...

Page 49: ...GNNE IGNNE AG23 IN INIT INIT AF08 IN LINT0 INT AF22 IN LINT1 NMI AF24 IN LOCK LOCK AE15 IN OUT N C A04 N C AB16 N C AC17 N C AC21 N C AD18 N C AE17 N C AG05 N C AG11 N C AG17 N C AG19 N C AG21 N C AH0...

Page 50: ...S2 AB08 IN RSP RSP AF06 IN SBSY SBSY AE13 IN OUT SBSY0 SBSY_C1 AA13 OUT SBSY1 SBSY_C2 AC19 OUT SMA0 SMA0 B18 IN SMBus signal SMA1 SMA1 A17 IN SMBus signal SMA2 SMA2 A15 IN SMBus signal SMSC SMSC B24 I...

Page 51: ...3 TUNER 2 TUNER 2 AG03 VCCMON VCCMON A11 OUT Power pod signal VCTERM VCTERM A02 IN VCTERM VCTERM A06 IN VCTERM VCTERM A10 IN VCTERM VCTERM A14 IN VCTERM VCTERM A18 IN VCTERM VCTERM A22 IN VCTERM VCTER...

Page 52: ...VCTERM VCTERM L24 IN VCTERM VCTERM N02 IN VCTERM VCTERM N06 IN VCTERM VCTERM N10 IN VCTERM VCTERM N14 IN VCTERM VCTERM N18 IN VCTERM VCTERM N22 IN VCTERM VCTERM R01 IN VCTERM VCTERM R04 IN VCTERM VCT...

Page 53: ...IN VCCMON VCCMON A11 OUT Power pod signal GND GND A13 IN VCTERM VCTERM A14 IN SMA2 SMA2 A15 IN SMBus signal GND GND A16 IN SMA1 SMA1 A17 IN SMBus signal VCTERM VCTERM A18 IN GND GND A19 IN GND GND A20...

Page 54: ...UT VCTERM VCTERM C12 IN N C C13 GND GND C14 IN N C C15 VCTERM VCTERM C16 IN D073 D73 C17 IN OUT GND GND C18 IN D070 D70 C19 IN OUT VCTERM VCTERM C20 IN D099 D99 C21 IN OUT GND GND C22 IN D097 D97 C23...

Page 55: ...5 IN OUT VCTERM VCTERM E06 IN D010 D10 E07 IN OUT GND GND E08 IN D040 D40 E09 IN OUT VCTERM VCTERM E10 IN STBP2 STBP2 E11 IN OUT GND GND E12 IN D039 D39 E13 IN OUT VCTERM VCTERM E14 IN D067 D67 E15 IN...

Page 56: ...N STBN6 STBN6 F22 IN OUT GND GND F23 IN D103 D103 F24 IN OUT GND GND F25 IN VCTERM VCTERM G01 IN GND GND G02 IN D014 D14 G03 IN OUT VCTERM VCTERM G04 IN D008 D08 G05 IN OUT D015 D15 G07 IN OUT VCTERM...

Page 57: ...77 H18 IN OUT GND GND H19 IN D111 D111 H20 IN OUT GND GND H21 IN D105 D105 H22 IN OUT GND GND H23 IN D109 D109 H24 IN OUT GND GND H25 IN GND GND J01 IN VCTERM VCTERM J02 IN D013 D13 J03 IN OUT GND GND...

Page 58: ...IN OUT GND GND K09 IN D050 D50 K10 IN OUT GND GND K11 IN N C K12 GND GND K13 IN N C K14 GND GND K15 IN D083 D83 K16 IN OUT GND GND K17 IN D080 D80 K18 IN OUT GND GND K19 IN D117 D117 K20 IN OUT GND GN...

Page 59: ...OUT GND GND M05 IN D028 D28 M06 IN OUT GND GND M07 IN D048 D48 M08 IN OUT GND GND M09 IN STBP3 STBP3 M10 IN OUT GND GND M11 IN D051 D51 M12 IN OUT GND GND M13 IN D084 D84 M14 IN OUT GND GND M15 IN ST...

Page 60: ...D GND N24 IN D119 D119 N25 IN OUT GND GND P01 IN D027 D27 P02 IN OUT GND GND P03 IN D024 D24 P04 IN OUT GND GND P05 IN D026 D26 P06 IN OUT GND GND P07 IN D054 D54 P08 IN OUT GND GND P09 IN D061 D61 P1...

Page 61: ...VCTERM R20 IN D124 D124 R21 IN OUT D126 D126 R23 IN OUT VCTERM VCTERM R24 IN D121 D121 R25 IN OUT GND GND T01 IN D030 D30 T02 IN OUT GND GND T03 IN DEP03 DEP3 T04 IN OUT GND GND T05 IN DEP02 DEP2 T06...

Page 62: ...N OUT VCTERM VCTERM U18 IN A027 AA27 xTPRValue0 U19 IN OUT GND GND U20 IN A048 AA48 AB48 U21 IN OUT VCTERM VCTERM U22 IN A042 AA42 AB42 U23 IN OUT GND GND U24 IN VCTERM VCTERM U25 IN GND GND V01 IN A0...

Page 63: ...AA37 AB37 W15 IN OUT A032 AA32 ATTR0 W17 IN OUT A030 AA30 xTPRValue3 W19 IN OUT A044 AA44 AB44 W21 IN OUT A046 AA46 AB46 W23 IN OUT A041 AA41 AB41 W25 IN OUT GND GND Y01 IN A007 AA07 EXF4 Y02 IN OUT G...

Page 64: ...AA33 ATTR1 AA17 IN OUT DBSY1 DBSY_C2 AA19 OUT GND GND AA20 IN DRDY1 DRDY_C2 AA21 OUT AP1 AP1 AA23 IN OUT GND GND AA24 IN AP0 AP0 AA25 IN OUT GND GND AB01 IN ID1 IDA1 IP1 AB02 IN GND GND AB03 IN ID5 ID...

Page 65: ...AC21 BPM3 BPM3 AC23 IN OUT GND GND AC24 IN BPM1 BPM1 AC25 IN OUT GND GND AD01 IN ID0 IDA0 IP0 AD02 IN GND GND AD03 IN ID4 IDA4 IDB4 AD04 IN GND GND AD05 IN ID8 IDA8 IDB8 AD06 IN GND GND AD07 IN RS1 RS...

Page 66: ...I AE25 IN GND GND AF01 IN TERM FSBT AF02 IN OUTEN OUTEN AF04 IN Power pod signal GND GND AF05 IN RSP RSP AF06 IN GND GND AF07 IN INIT INIT AF08 IN GND GND AF09 IN REQ1 WSNP D C LEN1 AF10 IN OUT GND GN...

Page 67: ...16 IN N C AG17 GND GND AG18 IN N C AG19 GND GND AG20 IN N C AG21 GND GND AG22 IN IGNNE IGNNE AG23 IN GND GND AG24 IN THRMTRIP THRMTRIP AG25 OUT Thermal trip GND GND AH01 IN TUNER 1 AH03 N C AH05 TDO T...

Page 68: ...68 Datasheet Pinout Specifications...

Page 69: ...the socket and the power pod and contains 611 pins which are positioned in a 25 x 28 grid The IHS which is mounted on the top surface of the processor package substrate efficiently transfers the heat...

Page 70: ...34 29 30 48 611 x 0 305 Pins Side View Integrated Heat Spreader Processor Package Substrate Interposer Pins 1 43 0 00 2 03 IHS Height See Note Substrate Height See Note Processor IHS Height Substrate...

Page 71: ...r Package Power Tab All dimensions are measured in mm Not to scale 001159a Top View Bottom View 46 96 42 21 46 00 2x 9 10 2x 12 91 4x R1 00 C L 2 98 12x 2 92 2x 25 85 C L 12x 38 76 90 00 45 00 42 46 2...

Page 72: ...O number Serial Number 4 2 2 Processor Bottom Side Marking The processor bottom side mark for the product is a laser marking on the pin side of the interposer Figure 4 5 shows the placement of the las...

Page 73: ...ix Mark only present on Itanium 2 processor 6 MB Itanium 2 processor 4 MB and Itanium 2 processor 1 3 GHz 3 MB Figure 4 5 Processor Bottom Side Marking Placement on Interposer 001267b Laser Mark inclu...

Page 74: ...74 Datasheet Mechanical Specifications...

Page 75: ...ails to control the processor temperature as this is affected by many factors such as cooling solution performance degradation and processor workload variations 5 1 1 Thermal Alert THRMALERT is a prog...

Page 76: ...above the normal operating temperature to ensure that there are no false trips The Itanium 2 processor will stop all execution when the junction temperature exceeds a safe operating level Warning Dat...

Page 77: ...Datasheet 77 Thermal Specifications Figure 5 2 Itanium 2 Processor Package Thermocouple Location All dimensions are measured in mm Not to scale 001103a Thermocouple Location 45 00 24 13...

Page 78: ...78 Datasheet Thermal Specifications...

Page 79: ...accurate means of acquiring an indicator of the junction temperature of the processor core die The thermal sensing device is connected to the anode and cathode of the Itanium 2 processor on die therma...

Page 80: ...eral understanding of the architecture 000668b Processor Information ROM A0 A1 A2 SC SD VCC 10K 10K 3 3V Scratch EEPROM A0 A1 A2 SD WP VCC SC 10K 10K 10K Thermal Sensing Device VCC A0 A1 SC SD STBY AL...

Page 81: ...i Z state for SMA2 the pin must be left floating The system should drive SMA1 and SMA0 and will be pulled low if not driven by the 10 k pull down resistor on the processor substrate Attempting to driv...

Page 82: ...Bit 1 Bit 0 A0h A1h 1010 0 0 0 X Scratch EEPROM 1 A2h A3h 1010 0 0 1 X Processor Information ROM 1 A4h A5h 1010 0 1 0 X Scratch EEPROM 2 A6h A7h 1010 0 1 1 X Processor Information ROM 2 A8h A9h 1010 1...

Page 83: ...en from CPUID 3 model 1Ah 8 Processor Core Stepping From CPUID Taken from CPUID 3 revision 1Bh 24 Reserved Reserved for future use 000000h 1Eh 16 Maximum Core Frequency Four 4 bit hex digits in MHz 1...

Page 84: ...dentification number May have padded zeros 4Dh 168 Reserved Reserved for future use x0h 62h 8 Checksum 1 byte checksum Add up by byte and take 2 s complement Thermal Reference 63h 8 Upper Temp Referen...

Page 85: ...shows the format of the random read SMBus packet The write with no data loads the address desired to be read Sequential reads may begin with a current address read or a random address read After the...

Page 86: ...sing device computes a byte of temperature data Software running on the processor or on a micro controller can use the temperature data from the thermal sensing device to thermally manage the system T...

Page 87: ...gister commanded by the last read byte packet If a receive byte packet was preceded by a write byte or send byte packet more recently than a read byte packet then the behavior is undefined Table 6 8 t...

Page 88: ...ter a conversion rate register and other reserved registers The following subsections describe the registers in detail 6 7 1 Thermal Reference Registers The processor core and thermal sensing device i...

Page 89: ...andby vs auto convert of the thermal sensing device Table 6 15 shows the format of the configuration register If the RUN STOP bit is set high then the thermal sensing device immediately stops converti...

Page 90: ...ister values and the conversion rate As indicated in Table 6 16 the conversion rate register is set to its default state of 02h 0 25 Hz nominally when the thermal sensing device is powered up There is...

Page 91: ...ET the processors sample the A 49 3 pins to determine their power on configuration A 1 2 A20M I A20M is ignored in the Itanium 2 processor system environment A 1 3 ADS I O The Address Strobe ADS signa...

Page 92: ...memory type Please refer to Table A 2 A 1 7 BCLKp BCLKn I The BCLKp and BCLKn differential clock signals determine the bus frequency All agents drive their outputs and latch their inputs on the diffe...

Page 93: ...hase except the Bus Invalidate Line BIL transaction A BIL transaction may return one cache line 128 bytes A 1 9 BERR I O The Bus Error BERR signal can be asserted to indicate a recoverable error with...

Page 94: ...us stall at the same time BNR is a wired OR signal In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is asserted and sampled on specific...

Page 95: ...ric agents is updated to the agent ID of the symmetric owner This update gives the new symmetric owner lowest priority in the next arbitration event A new arbitration event occurs either when a symmet...

Page 96: ...a Itanium 2 processor is not installed A 1 18 D 127 0 I O The Data D 127 0 signals provide a 128 bit data path between various system bus agents Partial transfers require one data transfer clock with...

Page 97: ...would have been indicated on HIT for a transaction which was not deferred DID 9 0 I O DID 9 0 are Deferred Identifier signals The requesting agent transfers these signals by using A 25 16 They are tr...

Page 98: ...transfer DRDY can be deasserted to insert idle clocks DRDY is replicated three times to enable partitioning of data paths in the system agents This copy of the Data Ready signal DRDY is an input as we...

Page 99: ...eration results Any bus agent can assert both HIT and HITM together to indicate that it requires a snoop stall The stall can be continued by reasserting HIT and HITM together A 1 37 ID 9 0 I The Trans...

Page 100: ...n the interrupt vector from the interrupt controller The LINT 0 pin can be software configured to be used either as the INT signal or another local interrupt A 1 42 IP 1 0 I The ID Parity IP 1 0 signa...

Page 101: ...her as NMI or as another local interrupt LINT1 pin A 1 47 OWN I O The Guaranteed Cache Line Ownership OWN signal is driven to the bus on the second clock of the Request Phase on the Ab 5 pin OWN is as...

Page 102: ...m execution at the reset vector A 1 52 RP I O The Request Parity RP signal is driven by the requesting agent and provides parity protection for ADS and REQ 5 0 Table A 10 Transaction Types Defined by...

Page 103: ...rrect parity A 1 55 SBSY I O The Strobe Bus Busy SBSY signal is driven by the agent transferring data when it owns the strobe bus SBSY holds the strobe bus before the first DRDY and between DRDY asser...

Page 104: ...ial input needed for IEEE 1149 1 compliant TAP A 1 62 TDO O The Test Data Out TDO signal transfers serial test data out from the Itanium 2 processor TDO provides the serial output needed for IEEE 1149...

Page 105: ...e TLB Purge transaction completes on the system bus A 1 67 TRDY I The Target Ready TRDY signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data tran...

Page 106: ...stem Bus IDS 1 GSEQ Low BCLKp Snoop Snoop Phase ID 9 0 Low BCLKp Defer IDS IDS 1 IDS Low BCLKp Defer Always INIT Low Asynch Exec Control Always1 NOTES 1 Synchronous assertion with asserted RS 2 0 guar...

Page 107: ...DID 9 0 Low BCLKp System Bus ADS 1 DRDY Low BCLKp Data Always DPS Low BCLKp System Bus ADS 1 DSZ 1 0 Low BCLKp System Bus ADS 1 EXF 4 0 Low BCLKp System Bus ADS 1 FCL Low BCLKp System Bus ADS 1 LEN 2...

Page 108: ...108 Datasheet Signals Reference...

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