Intel i845-PE, User Manual, Page: 39 / 86

BIOS
Page 4-9
DRAM RAS# to CAS# Delay
This item sets the timing parameters for the system memory such as the CAS (Column
Address Strobe) and RAS (Row Address Strobe). The default is by DRAM SPD.
Options: 2, 3.
DRAM RAS# Precharge
This item refers to the number of cycles required to return data to its original
location to close the bank or the number of cycles required to page memory before
the next bank activate command can be issued. The default is by DRAM SPD.
Options: 2, 3.
System BIOS Cacheable
This item allows the system to be cached in memory for faster execution.
Options: Disabled, Enabled.
Video BIOS Cacheable
This item allows the video to be cached in memory for faster execution.
Options: Disabled, Enabled.
Delayed Transaction
The mainboard’s chipset has an embedded 32-bit post write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification
version 2.2. The default is Enabled.
Options: Disabled, Enabled.
Command Per Clock
Enabling this item improves performance. The default is Auto.
Options: Auto, Enabled, Disabled.
Fast CS#
When set to “Enabled” and SDRAM is idle, CS# is asserted in the same time the
SDRAM tracking transitions to active state. The fast CS# timing is also applicable
for pipelined assertion that follows page hit cycle.
Auto: This selection will Auto detect.
Disabled: Normal CS# mode (CS# active two clocks after internal SDRAM-start
indication)
Enabled: Fast CS# mode (CS# active one clocks after internal SDRAM-start
indication)