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Summary of Contents for EV80Cl96KB

Page 1: ...EV80Cl96KB Evaluation Board User s Manual bier Number 270738 O ...

Page 2: ...EV80C196KB Microcontroller Evaluation Board Release 001 February 20 1989 ...

Page 3: ...your order The following are trademarks of Intel Corporation and its affiliates and may be used only to identify Intel products 376 Above ActionMedia BITBUS Code Builder DeskWare Digital Studio DVI EtherExpress ETOX ExCA FaxBACK Grand Challenge i i287 i386 i387 i486 i487 i750 i860 i960 ICE itBX Inboard Intel lnte1287 lntel386 lntel387 lntel486 lntel487 intel inside Intellec iPSC iRMX iSBC ISBX iWa...

Page 4: ... Configuration Jumper Locations Figure 3b 15 Expansion Ports Connectors and LEDs Locations Figure 4 16 Host Serial Connector Figure 5 17 8OCl96KB Serial Port Connector Figure 6 17 Analog Input Connector Figure 7 18 I O Expansion Connector Figure 8 18 Memory l O Expansion Connector Figure 9 19 Power Supply Connector Figure 10 19 25pin to g pin Adapter Figure 11 20 INTRODUCTION TO iRISM iECM96 SOFTW...

Page 5: ...2 STRING Commands 42 Processor Variables 43 ASSEMBLY AND DISASSEMBLY 44 Single Line Assembly Commands 44 Disassembly Commands 45 SYMBOL OPERATIONS 46 RISM 47 RISM Variables 47 RISM Structure 48 Receiving Data from the Host 48 Sending Data to the Host 48 RISM Commands 49 Schematics and Parts List Appendix A Specific iRlSM Information 0 Appendix B Listing of IRISM 196KB a e a Appendix C Timing Analy...

Page 6: ... 8 EV80C196KB Microcontroller Evaluation Board User s Manual Figure 1 EV8OCl96KB Evaluation Board ...

Page 7: ...d by removing jumper shunt El 6 12VDC 20 15mA 12VDC 20 15mA Upon power up or after a reset the board goes through initializations and a shift ing pattern is displayed on the Port 1 LEDs when initialization has completed prop erly Connecting to your PC Once you have applied power to the board you need to connect Pl to a PC serial port Pl is configured to interface pin to pin with a standard nine pi...

Page 8: ...16 bit embedded microcontroller Being a member of the MCW 96 family the 8OC196KB uses the same powerful instruction set and the same architecture as the existing MCS 96 products The 8OC196KB is an enhanced CMOS version of the 8097BH Its enhancements include up down and capture modes on Timer2 multiplyin nearly twice as fast Hold Ho d Acknowledge logic and power down and idle modes 9 speeds almost ...

Page 9: ...h buffer drivers which allow you to quickly observe the state of Port 1 HSO 0 and Port 2 5 PWM see figure 4 or the schematics in appendix A for loca tion The TxD and RxD pins of the 80C196KB Port 2 0 and Port 2 1 are con nected to RS 232 buffer drivers which are connected to P2 All of the I O signals are available on JP2 see figure 8 or the schematics in appendix A for pinout Note because RxD is c...

Page 10: ...grammable logic array which is socketed to allow easy changes For the sake of convenience it will be referred to as the EPLD throughout this text The EPLD uses latched addresses A8 Al5 along with CLKOUT HLDA RESET and STALE STretched ALE from the 8OCl96KB as decode inputs There are 4 enable outputs from the EPLD all of which are low level true however only one should be true at a time to avoid bus...

Page 11: ...chine will transition out of async start on the next rising edge of CLKOUT The next state entered depends on how many wait states are needed If only one is required the next state is remove old where WAIT is deasserted regardless of the inputs to the EPLD If two watt states are needed the next state is hold 2 where WAIT is always asserted then the state after that is remove hold The additional sta...

Page 12: ...errupt Signal to 8OC196KB A B UART Interrupt EXTINnP2 2 B C UART lnterrutp NMI El6 LED Driver Enable L E20 Enable RESET signal from host A B Enabled i 1 A B RESET from P2 __ Disabled B C RESET from Pl mm Reset circuit insolated E6 80C196KB CDE U5 pin 14 El1 HLDA Input to PLD U12 A B CDE Vss A B HOLD HLDA feature in use B C CDE Vcc HOLD HLDA not used El9 8OC196KB RXD signal from P2 A B RXD driven b...

Page 13: ...n27 A15 Pin 27 WRH Pin27 A15 Pin 27 WRH R C Pin 26 Vcc El2 U13 pin 27 El7 U14 pin 26 A B Pin27 A15 L t A B Pin26 A13 B C Pin 27 WRL k B C Pin 26 Vcc El3 U6 U13 pin 1 El8 U14 pin 27 A B Pin 1 A15 A B Pin27 A14 B C Pin 1 Vcc B C Pin 27 WR El4 U6 U13 pin 26 El5 U14 pin 1 A B Pin26 A14 A B Pin 1 A14 B C Pin 26 Vcc Figure 3b B C Pin 1 Vcc Memory Configuration Jumper LocationiD Pin 1 A15 ...

Page 14: ...3 P1 2 4 P1 3 5 P1 4 6 P1 5 7 P1 6 r JP2 input Output Expansion Connector 6 P1 7 9 P2 5 PWM 10 HSO O Ir JPl Analog Input Connector JP3 Memory i O Expansion Connector L JP4 Power Connector Pl 82510 External UART Port P2 8OC196KB Internal UART Port Figure 4 Expansion Ports Connectors and LEDs ...

Page 15: ...t Ready RTS Request To Send CTS Clear To Send RI Ring Indicator DTR Pl pin 4 CTS Pl pin 8 RTS Pl pin 7 Run Indicator P2 Serial Port Connector DB 9S RS232 L r L Figure 5 Pin Nos 5 VW 4 CD 3 VW 2 W 1 CF Host W 232 Signal Name SG Signal Ground DTR Data Terminal Ready TxD Transmit Data RxD Receive Data DCD Data Carrier Detect Connection on Evaluation Board Digital Ground INIT thru E20 A RxD of 8OC196K...

Page 16: ... VREF 18 Analog Channel 5 20 Analog Channel 6 22 VREF 24 Analog Channel 7 26 ANGND 2 Pl OBi directional 4 Pl l Bi directional 6 P1 2 Bi directional 8 P1 3 Bi directional 10 P1 4 Bi directional 12 Pl YBREQ Bi directional 14 Pl G HLDA Bi directional 16 P1 7 HOLD Bi directional 18 P2 0 Txd Output 20 P2 1 Rxd Bi directional 22 P22 Extint Input 24 P2 3fl2CLK Input 26 P2 4fl2RST Input 28 P2 5 PWM Output...

Page 17: ...7 vcc ___ 59 r I I I I I I I I I I I I I I I 7cl 70 70 7u 70 30 3u q u q u q u q u q u q u q u q u q u q u q u q u q n q u q u q u q u q u q u q u q u q u q u 2 vcc 4 DOBi directional 6 Dl Bi directional 8 D2 Bi directional 10 D3 Bi directional 12 D4 Bi directional 14 D5 Bi directional 16 D6 Bi directional 18 D7 Bi directional 20 vss 22 D8 Bi directional 24 D9 Bi directional 26 DlO Bi directioal 2...

Page 18: ... 2o EV80C196KB Microcontroller Evaluation Board User s Manual To Evalboard Note Signal mneumonics are reference to the host To host PC Figure 11 25pin to g pin Adapter ...

Page 19: ...of the ECM and the target system was easily achieved This allows you to interrogate and carefully modify the state of the target system while it is running This manual section describes the user interface provided by the iECM 96 the interface between this PC resident software and the target resident software and the structure of the software in the target Appendix B lists the resources of the 80C1...

Page 20: ...plementation dependent See appendix B or C for further information An asynchronous serial port capable of operation at 9600 baud must be available in the target system The RISM described in this document uses an Intel 82510 UART This version also uses the NMI Non Maskable Interrupt to signal that a received data character is available 1 The TRAP instruction is reserved Breakpoints and program step...

Page 21: ...o describe a class of computer architectures The RISM consists of about 300 bytes of MCS 96 code which provide primitive opera tions Software running in the host uses the RISM commands to provide a complete user interface to the target system The advantage of this approach is that the ECM can be readily adapted to different target systems and requires only a small part of the available target memo...

Page 22: ...the symbol is ambiguous then it will not be accepted by the parser The probability of ambiguous references can be reduced by specifying the module name along with the symbol name The module name must be preceded with a colon If a variable TEMP is declared both in MODULE1 and in MODULE2 then a refer ence to the TEMP declared by MODULE1 would be MODULEl TEMP PLM 96 or C 96 line numbers can be called...

Page 23: ... iECM 96 detects valid CTS Clear To Send and DSR Data Set Ready signals from the appropriate COM port it will sign on and display a command prompt If the target is stopped the command prompt will be an asterisk If the target is already running the prompt will be a greater than sign 5 DIAG If CTS or DSR are not present iECM 96 will complain about it and ask if you want to proceed or exit It is poss...

Page 24: ...oked in the diagnostic mode it will tell you to enter characters on the keyboard These characters will be sent to the target and the response from the target will be displayed on screen This is a simple confidence check on the serial communication channel You are told to enter a slash or re verse slash to terminate this mode and proceed in either the diagnostic mode or the normal user s mode If th...

Page 25: ...from B to C for this command to work properly This command operates by dropping the DTR modem control line This comes into the target as DSR After dropping DTR the iECM 96 software will wait about 1 second to allow the target to complete its initialization routines The iECM 96 will politely warn of this time delay and then ignore the user until it expires Unless special precautions are taken in th...

Page 26: ...iately following the last digit of the number with no interven ing space BASE This command will display the current default base BASE cvalid base This command will set the current default base to valid base When entering this command it is advisable to use an override character to select the new default base BASE 1 00 selects octal BASE 1 OT selects decimal BASE 1 OH selects hexadecimal This avoid...

Page 27: ...nformation contained in the HEX file The iECM 96 commands which operate on object files are LOAD filename LOADSYM filename SAVE caddr TO addr IN filename The metasymbol filename means that a valid MS DOS file name must be entered in that position of the command string LOAD filename This command loads the content records of the object file filename into the target memory and loads any associated sy...

Page 28: ...ample iECM 96 session for you to invoke and become more familiar with the features of iECM 96 Appendix G is a printout of DEMO LST which was created by turning on the list feature and invoking DEMO LOG by typing include demo log CR at the iECM 96 prompt The list and log files commands allow for default filenames and allow either overwrit ing existing data in the file or appending data at the end o...

Page 29: ... user and the responses generated by iECM 96 will be re corded in the file LOG This command behaves like the LOG filename command described below except that it uses the last filename that was entered as part of a LOG filename com mand If no such command has been entered then the default filename LOG ECM will be used LOG filename This command will attempt to open filename as a writable file If a f...

Page 30: ...nt the user s program counter so that it points at the original instruction The user s program will appear to stop execution immediately before executing the instruction with a breakpoint set on it All the TRAPS will be removed from the user s code and the original code restored Note Most monitor programs similar to iECM 96 display a message on the console when a break occurs e g Program break at ...

Page 31: ...ific breakpoint specified by cbp number to the value code addr Program Execution These commands start and stop execution of user code The commands provided are 2 FOREVER GO FROM code addr GO FROM code addr FOREVER GO FROM code addr TILL code addr GO FROM ccodezaddr TILL code addr OR code addr GO TILL code addr AqflLL code addr OR code addr If a GO with breakpoint command is entered the user code b...

Page 32: ...using the current breakpoint array GO FROM code addr FOREVER This command loads the user s PC with code addr clears the breakpoint array and starts execution of the user s code GO FROM code addr TILL code addr This command lo the user s PC w hthe code addr which follows the FROM keyword sets the first breakpoint BP O to the code addr which follows the TILL keyword and then starts execution of the ...

Page 33: ...proach is to use the GO command to execute to a specified breakpoint and then step through the code being tested looking for proper operation iECM 96 implements the step operation by using the TRAP instruction To step over a given instruction iECM 96 determines all the possible subsequent instructions and places TRAPS at these locations After doing this it allows the user s program to execute unti...

Page 34: ... of the actual step operation the SS and STEP commands beha ie the same They will be described together and will be called single step ping STEP 1SS This command single steps one time STEP 1SS count This command single steps count times STEP 1SS FROM code addr This command loads the user s pc PC with code addr and then single steps one time STEP 1SS FROM code addr count This command loads the user...

Page 35: ...address which is evenly divisible by 4 This more restrictive alignment rule will only apply to iECM 96 commands when using the single line assembler REAL A REAL is a 32 bit binary floating point number which conforms to the FPAL96 definition The 32 bits contain a sign bit an 8 bit exponent field and a 23 bit fraction field iECM 96 commands use standard scientific notation to deal with REAL num ber...

Page 36: ...ing its current value When invoked this command sets the BYTE variable at byte address to byte value BYTE byte address TO cbyte_address This form is used to display a region of memory as a sequence of BYTE variables When this command is invoked iECM 96 will start by displaying the current default base and then a series of lines showing the contents of the selected memory region 16 a symbol exists ...

Page 37: ...king its cur rent value When invoked this command sets the WORD variable at word address to word value WORD word address TO word address This form is used to display a region of memory as a sequence of WORD vari ables When this command is invoked iECM 96 will start by displaying the current default base and then a series of lines showing the contents of the selected memory region If a symbol exist...

Page 38: ...cking its current value When invoked this command sets the DWORD variable at cdword address to cdword value DWORD cdword address TO cdword address This form is used to display a region of memory as a sequence of DWORD vari ables When this command is invoked iECM 96 will start by displaying the current default base and then a series of lines showing the contents of the selected memory region If a s...

Page 39: ...le without first checking its current value When invoked this command sets the REAL variable at real address to real value REAL real address TO real address This form is used to display a region of memory as a sequence of REAL variables When this command is invoked iECM 96 will display a series of lines showing the contents of the selected memory region If a symbol exists in iECM 96 s symbol table...

Page 40: ...mand is invoked iECM 96 executes a WORD word address TO word address command where both word address fields are formed by adding the corresponding stack address to the current value of the system stack pointer During lengthy displays you can stop the output to the console by hitting the SPACE bar Display can be resumed by hitting the SPACE bar a second time The command can be terminated by enterin...

Page 41: ... the user the user must still allow for the extra stack space used This is convenient but creates confusion if you display using the SP command and then use the WORD command to look at location 18H which is the register address of the stack pointer Location 18H will be 4 less than SP An additional consideration is what happens when you attempt to write into the stack pointer using the SP command B...

Page 42: ...ic instructions the MCS 96 processors understand SLA Single Line Assembly Commands The commands which invoke the SLA are I44 code address The SLA is useful for writing short code pieces on line for testing or patching pro rams 9 but is not intended as a replacement for a true assembler such as ASM 96 he SLA can be invoked whether or not user code is running but there is an obvi ous danger in modif...

Page 43: ...During lengthy displays you can stop the output to the console by hitting the SPACE bar Display can be resumed by hitting the SPACE bar a second time The command can be terminated by entering a carriage return DASM code_addr This command disassembles the instruction at code addr The parameter code addr must be greater or equal to 256T 1OOH so that the command parser can distinguish it from the DAS...

Page 44: ...affecting the target s memory This command is described in the section File Operations SYMBOLS This command displays the symbols that are currently in iECM 96 s symbol table SYMBOLS OFF This command suppresses searching the symbol table during output It does not prevent the use of the symbol table during input This command is provided be cause symbolic output with large symbol tables can be very s...

Page 45: ...wing Boolean flags DLE FLAG Thisflag indicates the next character received by the RISM should be treated as a data byte even if its value corresponds to an implemented command RUN FLAG This flag indicates that the target is running user code TRAP FLAG This flgg indicates that the target was running user code but that a software TRAP occurred which suspended its execution DIAGNOSTIC FLAG This is an...

Page 46: ...m the Host When the RISM receives a character from the host its first task is to determine if it represents a command or data If the character is less than 32 decimal then it is assumed to be a command if not then it is taken to be data If the host needs to send a data byte which has a value less than 32 then it first must issue a SET DLE command If the DLE FLAG is set then the next character rece...

Page 47: ...s command will read the word of memory pointed to by the RISM ADDR register and place the result in the least significant word of the RISM DATA register READ DOUBLE Code 06H This command will read the double word of memory pointed to by the address register and place the result in the RISM DATA register WRITE BYTE Code 07H This command stores the least significant byte of the RISM_DATA register in...

Page 48: ...ser s code from the RISM DATA register The host software will only invoke this command while user code is not running START USER Code 0x12 This command is responsible for starting the execution of user code clearing the TRAP FLAG and setting RUN FLAG The action of this command relies on it being executed as part of an ISR interrupt service routine At the start of the ISR the current PC and PSW are...

Page 49: ...e whenever it detects the ring indicator and will only issue REPORT STATUS commands if the ring indicator is off MONITOR ESCAPE Code 0x15 This command provides for the addition of RISM commands for special purposes it uses the RISM DATA register to extend the command set of the RISM The basic RISM requires only one of these extended commands if the lower 16 bits of the RISM DATA register is one RI...

Page 50: ...Appendix A Schematics and Parts List ...

Page 51: ... Y C e ...

Page 52: ......

Page 53: ...t t ...

Page 54: ......

Page 55: ...MIREF02 Hamilton PM1 PEFOZHP LM358N Hamilton diode Hamilton 811N4305 resistor Sterling Dale MDP 1603 271G cap Hamilton Sprague 926CX7R562KOSOB 12MHz Sterling M TRON MP 1 12 0000 18 432MHz Sterling M TRON MP 1 18 4320 RESET Digi key Panisonic P9950 184305 Hamilton lN4305 HDSP 48XX Sterling Lite On LTAlOOOG 180 Hamilton Mepco CR25 180 4 7K Hamilton Mepco CR25 4 7K 1OK Hamilton Mepco CR25 1OK 1OOK Ha...

Page 56: ...16 42 43 44 45 46 c29 Pl P2 E2 E16 E19 E7 El E3 E4 ES E6 E8 E9 E10 Ell E12 E13 E14 El7 E18 E20 El5 JP4 JPl JP2 JP3 22uF DB9 Female 2PIN JUMPER 3PIN JUMPER Hamilton Sprague lSOD226X9015B2 Sterling AMP 207084 l Marshall A P Prod Marshall A P Prod 4PIN JUMPER Marshall A P Prod POWER CONNECTOR Hamilton Molex 09 74 1041 CON26 Marshall A P Prod 929665 01 36 CON50 Marshall A P Prod 929665 01 36 CON60 Mar...

Page 57: ...Appendix B Specific iRlSM Information ...

Page 58: ...h to run code in the board while it is not connected to a host you should remove jumper shunt E20 prior to disconnecting the board from the host If E20 is left installed the board may reset as the connec tion is broken Reserved Memory User ROMsim as shipped is 24K bytes from address 2000H to 7FFFH The board is reconfigurable to accept various memory devices However breakpoints and pro gram steppin...

Page 59: ...Appendix C Listing of iRISM 196KB ...

Page 60: ...ART 82510 with the received data interrupt tied to the NM1 Non Maskable Interrupt of the processor i The use of the NM1 for this purpose allows the user to maintain control of the system even if the running program locks out the interrupts or modifies the mask register In addition to the NM1 and its vector this RISM uses the following resources Two words in the system stack i The TRAP instruction ...

Page 61: ...Zero Register ad command ad result lo abresult hi hsi mode hsi time hso time hsi status hso command sbuf int mask int pending spcon spstat watchdog timer1 timer2 port0 baud reg ioportl ioport2 ioc0 ios0 iocl iosl pwm control sP A to D command register Low byte of result and channel High byte of result Controls HSI transition detector HSI time tag HSO time tag HSI status register reads fife HSO com...

Page 62: ...veral macros generate specifically for this program _ _ ENTER RISM i A macro which generates the prologue for the RISM ISR i EXIT RISM A macro which generates the epilogue for the RISM ISR SEND DATA BYTE i A macro which passes the lower eight bits of RISM DATA to the serial port it assumes the port is ready for data BYTE PROTECT i A macro which terminates the RISM ISR if the RISM is about i to wri...

Page 63: ......

Page 64: ...58 OOlC 159 OOlD 160 OOlE 161 0020 162 0022 163 164 165 01 24 89 13 55 41 PAGE 5 SOURCE STATEMENT These registers are used only by the diagnostic routines They are not required for normal execution rseg at lch i ___ i ax dsw 1 al equ ax byte ah equ axtl byte dx dsw 1 bx dsw 1 cx dsw 1 ie ject ...

Page 65: ...ISM address register tempw dsw 1 Temp for use by monitor tempb w tempwzbyte char ew tempw byte RISM STAT dsb 1 Contains rism state flags DEFINE BIT DEFINE BIT DLE FLAG 0 DEFINE BIT RUN FLAG 2 TRAP FLAG 1 DEFINE BIT USER MAP 3 DEFINEIBIT DIAGNOSTIC FLAG 7 These variables are used by the monitor when in diagnotic mode only dUSER_PC dsw 1 Saves user s pc during halt dUSER PSW dsw 1 Saves user s psw d...

Page 66: ...rtt6 byte bank0 uartt7 byte bank0 uart byte bank3 uartt4 byte bank3 The memory map of the board is changed by reading or writing to an address between lOOOH and 1DFFH In this code this is accomplished by branching to address lOOOH to continue RISM execution The memory map of this board both before and after RESET are as follows Address OOOO OOFFH as data Internal Reg file OOOO OOFFH as code RISM M...

Page 67: ... points for routines which may be loaded into RAM in the diagnostic mode i In the diagnostic mode memory at the interrupt vectors is mapped to EPROM i so it is not possible to write into the vector table In the normal i e non diagnostic mode the interrupt vector table is i mapped to RAM so the vectors can be loaded as part of the normal process of loading a user s object code timer overflow dew 40...

Page 68: ...6 AOBS C701021E36 ldb tempb 60H stb tempb general int O set up uart line config reg for no par 1 stop Ebit and txd rxd access switch to bank3 i AOBA 815036 AOBD C701001E36 ldb tempb 50H select baud rate gen a for both stb tempb clock confg O rx and tx clock source AOC2 B17F36 AOC5 C701041E36 ldb tempb X7FH stb tempb io mode O select OUT1 mode on pin 12 AOCA C701021EOO stb zero general int O switch...

Page 69: ... tested for the set user command I or the set diagnostics command If either command was sent it is carried out If the diagnostic flag is set the program branches to the diag mode code ___ ___ ___ not user bbs stb inch stb decb cmpb be cmpb I bne RISM STAT DIAGNOSTIC FLAG diag mode char ioportl splash received char on leds char send back incremented char char txd rxd Ol char char J marks end of ser...

Page 70: ...ext RESET or RISM STAT gets altered somehow The user s PC is loaded with the address of the memory test and a 55H OAAH pattern flashes on the ioportl LEDs while the monitor is waiting for a command set diag SET BIT RISM STAT DIAGNOSTIC FLAG Id sp ltlOOH clear stack Id tempw trism psw value for rism and initial user value st tempw dUSER PSW store rism psw as initial user psw Id tempw mem tst offset...

Page 71: ...7F7DE A13E A13E C3636 A141 643636 Al44 A3374C2136 Al49 E336 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 the diagnostics mode ________________________________________ diag mode 0 bbs RISM STAT DLE FLAG force load data cmpb char lFH check if byte is a command I bh load data commands are 1FH diag command ldbze tempw char table lookup add tempw tempw Id tempw diag table offset tempwj b...

Page 72: ...46 447 448 449 OUK E jTA I EMENT llaq t able dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew Seject SET DLE FLAG offset 00 exit offset 01 TRANSMIT offset 02 exit offset 03 READ BYTE offset 04 READ WORD offset 05 READ DOUBLE offset 06 WRITE BYTE offset 07 WRITE WORD offset 08 WRITE DOUBLE offset 09 LOAD ADDRESS offset OA INDIRECT ADDRESS offset OB dREAD_PSW o...

Page 73: ...tics mode dSTART_USER _ Flush the pause routine off the stack and set up user s context SET BIT RISM STAT RUN FLAG CLR BIT RISM STAT TRAP FLAG stb RISM STAT modem contr Ol update running signal to host add sp 4 push dUSER PC push dUSER PSW EXIT RISM reset sp to overwrite RISM pc psw with user pc user psw values TOP USER i stops user execution by setting up the stack to return to pause with i all i...

Page 74: ...lA A03A30 506 507 AlAE 510 AlAE A3180230 511 512 515 516 iOURCE STATEMENT WRITE PC user pc RISM DATA Assumes user code is not running St RISM DATA dUSER_PC EXIT RISM BREAD PC _ RISM DATA user pc bbs RISM STAT RUN FLAG drpc running Id RISM DATA dUS ER PC If user code is not running EXIT RISM drpc running Id RISM DATA 2 spl If user code is running EXIT RISM ie ject ...

Page 75: ...1 24 89 13 55 41 PAGE 16 SOURCE STATEMENT dREAD PSW RISM DATA user psw bbs RISM STAT RUN FLAG drpsw running Id RISM DATA dUSER PSW user is not running EXIT RISM drpsw running Id RISM DATA sp user is running EXIT RISM dWRITE_PSW _________ i user psw RISM DATA bbs RISM STAT RUN FLAG dwpsw running st RISM DATA dUSER_PSW user is not running EXIT RISM dwpsw running St RISM DATA spl user is running EXIT...

Page 76: ...is useful to see if the board is executing code properly If a or is received from the host while this routine is executing it will terminate immediately i Id fl wait0 bbc bbc fl loopl shl stb fl waitl bbc bbc cv bne cw bne br quit ldb ret Seiect 586 rism addr OFFH iosl 5 _ fl wait0 iosl 5 wait for a timer1 overflow twice rism addr l shift another 1 into or out of risk addrtl ioportl ioportl iosl 5...

Page 77: ...enting and decrementing the test data on even and odd cycles of the test so that a nonrepetitive pattern is produced in memory loop i here ldb clr clr clr clrb Id stb cmpb bne bbc decb br inch around cw bne Id inc inch ldb br failed Id br Seject _ iocl OlH ax CX dx ioportl bx t2800H al bxl al bx failed dx 0 here al around al bx 8000H loop bx t2800H dx ioportl pwm control loop CX OFFFFH s enable PW...

Page 78: ... 663 iOURLE STATEMENT cseg at offset 22808 cycle byte _ __ does alternate read and write operation on the byte specified by bx _ __ ___ __________________________ CLR BIT IOPORT1 7 cb loop SET BIT IOPORT1 7 stb ax bxl CLR BIT IOPORT1 7 ldb ax l tbxl br cb loop cseg at offset 22AOH __ _ _ cycle word _ _ does alternate read and write operation on the word specified by bx __ _________ __ _ CLR BIT IO...

Page 79: ... at offset t 1DOOH user setup ___ This code completes changing the board into user mode The PLD on the board U12 automatically remaps memory when code from this address range is fetched Id tempw Irism psw value for rism and initial user value st tempw USER PSW store rism psw as initial user psw Id tempw 12080H Set up user pc St tempw USER PC Id tempw break offset st tempw trap offset O initialize ...

Page 80: ...m contr O update running signal to host add sp 4 reset sp to overwrite RISM pc 6 psw push USER PC push lJSER PSW EXIT RISH with user pc h user psw values break I This routine is invoked by a TRAP instruction used for breakpointing it operates somewhat like a STOP USER instruction ENTER RI SET BIT RISM STAT TRAP FLAG bbs RISM STAT DIAGNOSTIC FLAG dSTOP_user STOP USER Stops user execution by setting...

Page 81: ...O 9D80 8600 9D82 221D 9D84 451D 9D86 COO0 9D88 4EOO dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew dew ieject SET DLE FLAG offset 00 exit offset i 01 TRANSMIT offset 02 exit offset 03 READ BYTE offset 04 READ WORD offset 05 READ DOUBLE offset 06 WRITE BYTE offset 07 WRITE WORD offset 08 WRITE DOUBLE offset 09 LOAD ADDRESS offset OA INDIRECT ADDRESS offset OB RE...

Page 82: ...i Control passes to this point when the rism gets a serial i o interrupt from the host system rism isr ENTER RISM ldb tempb general int O read uart interrupt status xorb tempb OOOOOlOOB test for receive fifo interrupt be receive ready ldb tempb XOlH enable only recieve fifo interrupt stb tempb gener enabl O of the uart mask all others exit EXIT RISM receive ready ldbze tempw txd rxd O char is low ...

Page 83: ...846 01 24 89 13 55 41 PAGE 24 WURCE STATEMENT force load data CLR BIT RISM STAT DLE FLAG load data shll RISM DATA f8 ldb RISM DATA char EXIT RISM SET DLE FLAG RISM STAT O SET SET BIT RISM STAT DLE FLAG EXIT RISM TRANSMIT utxd RISM_DATA 7 0 RISM DATA RISM DATA 8 RISM ADDR RISM ADDR l SEND DATA BYTE shrl RISM DATA X8 inc RISM ADDR EXIT RISM MONITOR ESCAPE if RISM DATA 1 then execute reset i cmp RISM...

Page 84: ..._ RISM DATA byte at RISM ADDR i Idb RISM DATA RISM ADDR EXIT RISM READ WORD RISM DATA word at RlSM ADDR Id RISM DATA RISM ADDRI EXIT RISM READ DOUBLE RISM DATA double word at RISM ADDR Id RISM DATA RISM ADDRI Id RISM_DATA 2 2 RISM_ADDR EXIT RISM WRITE BYTE _ __ _ i byte at RISM ADDR RISM DATA RISM ADDR RISM ADDR l BYTE PROTECT stb RISM DATA RISM ADDR i EXIT RISM WRITE WORD i word at RISM ADDR RISM...

Page 85: ...9 950 951 954 955 01 24 89 13 55 41 PAGE 26 SOURCE STATEMENT LOAD ADDRESS RISM ADDR RISM DATA Id RISM ADDR RISM DATA EXIT RISM INDIRECT ADDRESS RISM ADDR RISM ADDRI Id RISM ADDR RISM ADDRI EXIT RISM WRITE PC __ usergc RISM DATA Assumes user is not running st RISM DATA USER PC EXIT RISM READ PC _ RISM DATA user pc i bbs RISM STAT RUN FLAG rpc running Id RISM DATA USER PC If user code is not running...

Page 86: ...SW RISM DATA user psw bbs RISM STAT RUN FLAG rpsw running Id RISM DATA USER PSW i user is not running EXIT RISM rpsw running Id RISM DATA spl user is running EXIT RISM WRITE PSW i user psw RISM DATA Assumes user is not running st RISM DATA USER PSW user is not running EXIT RISM READ sP RISM DATA user sp add RISM DATA sp t4 EXIT RISM i WRITE SP add four to account for PC and PSW on the stack during...

Page 87: ... 0020H A283H 0036H A018H lEOOH 9D5EH A2A3H 0022H A280H AZAOH A13EH A130H A122H A125H Al4CH 0007H 00OOH AlACH AlB4H AlAEH AlBCH A191H A178H A18DH 003AH 003CH AlC9H AlAlH AlClH NULL ABS BYTE CODE ABS WORD NULL ABS BYTE NULL ABS BYTE DATA ABS BYTE REG ABS BYTE REG ABS BYTE CODE ABS ENTRY REG ABS WORD DATA ABS BYTE DATA ABS BYTE NULL ABS BYTE MACRO CODE ABS ENTRY REG ABS WORD MACRO CODE ABS ENTRY REG ...

Page 88: ...0006H 0004H AOOBH 0006H A006H 000411 8081H 0008H 0009H A012H lE04H 0015H 0016H OOOFH OOlOH 0015H 0016H lE03H lE05H 807CH 8035H AZOFH A200H lE04H lE06H 804EH 9D20H A03EH AOE4H CODE ABS ENTRY REG ABS WORD MACRO MODULE MAIN STACKSIZE CODE ABS ENTRY MACRO CODE ABS WORD CODE ABS WORD CODE ABS ENTRY CODE ABS ENTRY CODE ABS NTRY CODE ABS ENTRY CODE ABS ENTRY CODE ABS ENTRY DATA ABS BYTE DATA ABS BYTE COD...

Page 89: ...OOOH OOOOH 0038H 8097H 80A7H OOOZH OOOlH 0007H AOOCH A032H A03OH AlODH 803DH 9D4DH AOOAH 0018H OOllH OOllH 9D22H 9D45H OOOOH 0036H 0036H AOOOH OOOAH OOOCH A036H A038H 80428 AOlOH OOOlH 0002H I TTRIBUTES NULL ABS NULL ABS BYTE CODE ABS ENTRY NULL ABS BYTE CODE ABS ENTRY CODE ABS ENTRY CODE ABS ENTRY CODE ABS ENTRY CODE ABS ENTRY CODE ABS ENTRY CODE ABS ENTRY CODE ABS ENTRY CODE ABS ENTRY CODE ABS E...

Page 90: ... JAI lIb IEUOH LEOOH 0003H 2020H 2022H 9DOOH OOOAH 806AH 80748 8086H EOACH 80BAH 806FH OOOOH 01 24 89 13 55 41 PAGE 31 A r l H LHlJTES DATA ABS BYTE DATA ABS BYTE NULL ABS DATA ABS WORD DATA ABS WORD CODE ABS ENTRY NULL ABS BYTE MACRO CODE ABS ENTRY CODE ABS ENTRY CODE ABS ENTRY CODE ABS ENTRY CODE ABS ENTRY CODE ABS ENTRY NULL ABS WORD ASSEMBLY COMPLETED NO ERROR S FOUND ...

Page 91: ...Appendix D Timing Analysis ...

Page 92: ...IT 10 ns AC11 2 CLOCK to Q Tplh MAX Tllyx is irrelevant in this design Tavgv 81 ns MAX Tclyx BUSWIDTH 11 ns AC373 Dn to On Tplh MAX 35 ns PAUEPLD Tpd MAX 46 ns Tllgv is irrelevant in this design Tclgx is irrelevant in this design Tavdv 183 ns MAX for zero wait states Tavdv ROMsim 11 ns AC373 Dn to On Tplh MAX 35 ns PAUEPLD Tpd MAX 100 ns RAM Tcol MAX 146 ns Tavdv 349 ns MAX for one wait state Tavd...

Page 93: ...X Trxdx 0 ns MIN Trxdx ROMsim 0 ns RAM Tohz MIN Trxdx EPROM 0 ns EPROM Toh MIN Trxdx UART is not specified Txhch is irrelevant in this design Tclcl 166 ns Tclcl WAIT 55 ns PAUEPLD Tp MIN 10 ns AC1 12 l Fmax MIN Tchcl 73 ns MIN Tchcl WAIT 25 ns PAUEPLD Tco MAX 35 ns PAUEPLD Tpd MAX 4 ns AC1 12 Tsu MIN 64 ns or 25 ns PAUEPLD Tco MAX 35 ns PAUEPLD Tpd MAX 8 ns AC08 Tplh MAX 2 ns AC1 12 Trem MIN 70 ns...

Page 94: ...t in this design Trlrh 411 ns MIN for two wait states Trlrh UART 281 ns UART Trlrh MIN Trhlh 83 ns MIN Trhlh STALE 9 ns 74AC08 Tplh MAX 3 ns 74AC112 Trem MIN 12ns Tllwl 73 ns MIN Tllwl UART 7 ns UART Tavwl MIN Tclwl is irrelevant in this design Tqvwh 60 ns MIN for zero wait states Tqvwh ROMsim 40 ns RAM Tdw MIN Tqvwh 393 ns MIN for two wait states Tqvwh UART 90 ns UART Tdvwh MIN Tchwh is irrelevan...

Page 95: ...IN 9 ns Twhqx U14 0 ns RAM Tdh MIN Twhqx UART 12 ns UART Twhdx MIN Twhlh 73 ns MIN Twhlh ROMsim 9 ns 74AC32 Tplh MAX 0 ns RAM Twr MIN 9 ns Twhlh UART 0 ns UART Twhax MIN Twtilh STALE 9 ns 74AC08 Tplh MAX 3 ns 74AC112 Trem MIN 12 ns Twhbx is irrelevant in this design ...

Page 96: ...Appendix E Programmable Logic Equations ...

Page 97: ... MCS96 RESET pin Output declarations OUTPUTS nCS510 14 QV enable uart U20 nCE2 15 OV enable U14 memory nBUSWIDTH 16 OV put processor in 8 bit mode SBO 17 wait state counter bit 0 SB1 18 wait state counter bit 1 nWAIT 19 OV hold MCS96 in wait state SB2 20 wait state counter bit 2 nCEO 21 OV enable Ul and U8 memory nCE1 22 OV enable U6 and U13 memory MAP 23 5V map RAM as romsim 3 0 3 0 I Architectur...

Page 98: ...3 STALE EPROM MAP RANGE61 RANGE1 RANGE4 RAM MAP RANGE6 RANGE7 EEPROM RANGE8 UART RANGE5 OPEN0 RANGE2 RANGElO OPEN1 RANGE9 nBWd EEPROM UART WAIT 1 STALE WAIT 2 STALE WAIT 3 WAIT 4 WAIT 4 WAIT 5 WAIT 5 WAIT 6 WAITIG WAIT 7 WAIT 7 GND nWAITd WAIT HLDA WAIT 2 EPROM OPENl HLDA WAIT 3 UART ...

Page 99: ...A14 A13 Al2 A11 A15 A14 A13 A12 A9 RANGE3 A15 A14 A13 Al2 A9 lOOO 1DFF A15 A14 A13 Al2 A10 A15 A14 A13 Al2 All RANGE4 A15 A14 A13 Al2 All A10 A9 A8 lDOO 1DFF RANGE5 A15 A14 A13 Al2 All A10 A9 A8 lEOO 1EFF A11 2000 27FF 2800 5FFF RANGE6 A15 A14 Al3 A12 RANGE7 A15 A14 Al3 Al2 A15 A14 Al3 All A15 Al4 A13 RANGE8 A15 Al4 A13 RANGE9 Al5 A14 RANGE10 Al5 A14 6000 7FFF 8000 BFFF COOO FFFF ...

Page 100: ...C START 0 0 0 10 Q 11 O 113 1 111 1 101 El cl 01 1 Q 11 O 101 IF WAIT 1 WAIT 2 THEN REMOVE HOLD IF WAIT 2 THEN HOLD 2 ASSERT IF WAIT 1 THEN WAIT IF WAIT 3 THEN HOLD 3 REMOVE HOLD ASSERT WAIT IF WAIT 4 THEN HOLD 4 REMOVE HOLD ASSERT WAIT IF WAIT 5 THEN HOLD 5 REMOVE GOLD ASSERT WAIT IF WAIT 6 THEN HOLD 6 REMOVE ZOLD ASSERT WAIT IF WAIT 7 THEN HOLD 7 REMOVE HOLD ASSERT WAIT REMOVE HOLD ASSERT WAIT A...

Page 101: ... CS510 PIN 15 CE2 PIN 16 BUSWIDTH PIN 17 state bit 0 PIN 18 state bitll PIN 19 WAITT PIN 20 state bit 2 IN 21 CEO IN 22 CEl PIN 23 MAP OV enable uart U20 OV enable U14 memory OV put processor in 8 bit mode wait state counter bit 0 wait state counter bit 1 OV hold MCS96 in wait state wait state counter bit 2 OV enable Ul and U8 memory OV enable U6 and U13 memory 5V map ram as romsim l Declarations ...

Page 102: ...hold 3 b 011 SDEFINE hold 4 b lll SDEFINE hold 5 b 110 SDEFINE hold 6 b 100 SDEFINE hold 7 b 101 SDEFINE remove hold b 010 Wait State Machine SEQUENCE state count PRESENT async start IF wait 1 OUT WAIT IF wait 1 wait 2 NEXT remove hold IF wait 2 NEXT DEFAULT hold 2 NEXT async start PRESENT hold 2 OUT WAIT IF wait 3 DEFAULT PRESENT hold 3 OUT WAIT NEXT hold 3 NEXT remove hold IF wait 4 NEXT DEFAULT...

Page 103: ...remove hold PRESENT hold 7 OUT WAIT NEXT remove hold PRESENT remove hold NEXT async start Logic Equations MAP D memaddr 1000 1DFF STALE MAP MAP AR RESET MAP SP b 0 MAP OE b l state bit O AR RESET state bit O SP b 0 state bit O OE b l state bit l AR RESET state bit l SP b 0 state bit l OE b l state bit 2 AR RESET state bit 2 SP b 0 stateIbitIZ OE b l CEO eprom CEl ram CE2 eeprom cs510 uart BUSWIDTH...

Page 104: ...Appendix F Standard Memory l O Connector for EvalBoards ...

Page 105: ... I 45 I 47 1L 49 1 I 51 L 53 I 55 _ 57 59 2 vcc 4 Addr Data 0 6 Addr Data 1 a Addr Data 2 10 Addr Data 3 12 Addr Data 4 14 Addr Data 5 16 Addr Data 6 la Addr Data 7 20 vss 22 Addr Data 8 24 Addr Data 9 26 Addr Data 10 28 Addr Data 11 30 Addr Data 12 32 Addr Data 13 34 Addr Data 14 36 Addr Data 15 38 vss 40 vss 42 WR 44 BHE 46 SRDY 48 DRQO 50 INTO 52 TOIN 54 HOLD 56 12VDC 58 vss 60 vcc vcc Addr Dat...

Page 106: ...Appendix G Sample Session ...

Page 107: ...Type ECM96 and carriage re turn At the asterisk prompt type INCLUDE DEMO LOG and carriage return For additional information please see the EV80C196KB Microcontroller Evaluation Board USER S MANUAL pause Hit the space bar to continue This command loads 96KBDEMO OBJ from disk load 96kbdemo obj mod name is IDFM096KBI mod date stamp is 01 24 89 16 34 47 f pause Hit the space bar to continue t dasm 208...

Page 108: ...B 17 IOPORTl 20B7 27DC I SJMP LOOP I FAILED 20B9 AlFFFF20 I LD CX OFFFF used while code is running on the board pause Hit the space bar to continue asm 20b2 start assembling code at address ZObZH see disassembly list 1qg Single Line Assembler activated exit with end directive 2OB2H decb ioportl 20B4H end pause Hit the space bar to continue The LED s for I O Port 1 should now be decrementing Note t...

Page 109: ...a breakpo pause Hit the space bar to continue int Ol 20a6H pc Code has stopped at the breakpoint Note that 20a6 has not executed yet PC PAST pause Hit the space bar to continue br This command displays all breakpoints 20a6 has been set BREAKPOINT O PAST oause Hit the space bar to continue l br Cij O This command clears breakpoint O oause Hit the space bar to continue br As can be shown NC BREAKPOI...

Page 110: ... Hit the space bar to continue This concludes the demo we hope you enjoy using the EV80C196KB board pause Hit the space bar to continue Type QUIT and carriage return to exit iECM 96 quit ...

Page 111: ...kane 99206 Tel 509 928 8086 FAX 509 926 9467 Suite 115 Oklahoma Cii 73182 Tel 405 648 8088 FAX 405 840 9619 tlntel Corp 10010 Junction Dr Suite 200 Annapolis Junction 20701 Tel 410 206 2860 FAX 410 206 3878 Intel Corp neNkautve Dr Brookiield 53005 Tel 414 789 2733 MeI cofp 15254 N W Greenbrier Pkwy Building B Beaverton 97008 Tel 503 8458051 TWX 910 467 8741 FAX 503 6458181 PENNSVLVANIA tlntel Corp...

Page 112: ...nd 23235 Tel 804 3309393 Intel Corp 155 106th Avenue N E Ste 386 Beflevue 98094 Tel 266 4538086 Intel Corp 3401 Park Center Dr Ste 226 CALIFORNIA ILLINOIS l TfnteI Corp Woodfield Corp Center Ill 300 N Martingale Rd Ste 400 Schaumburg 60173 Tel 708 8058031 INDIANA Intel Corp 21515 Vanowen St Ste 116 canoga Park 91303 Tel 816 704 8506 MISSOURI Fih celP Dr Ste 1W Tel 218 4 84 2738 vltel Corp 3300 Rid...

Page 113: ...shire England SN3 1RJ GERMANY Intel GmbH Domacher Strasse 1 85622 FeldkircherVMuenchen HONG KONG Intel Semiconductor Ltd 32 F Two Pacific Place 88 Queensway Central CANADA Intel Semiconductor of Canada Ltd 190 Attwell Drive Suite 500 Rexdale Ontario M9W 6H8 Intel embedded architectures and flash memory are supported by au array of development tools solutions Use the World Wide Web FaxBack Literatu...

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