Intel Cougar Canyon 2 Platform Manual Download

Page: 1 / 25

3rd Generation Intel

Core™

Processor with Mobile Intel

HM76/QM77 Express Chipset

Customer Reference Board

Platform Guide

September 2014

Document Number: 331208-001

Summary of Contents for Cougar Canyon 2

Page 1: ...3rd Generation Intel Core Processor with Mobile Intel HM76 QM77 Express Chipset Customer Reference Board Platform Guide September 2014 Document Number 331208 001 ...

Page 2: ...RNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future...

Page 3: ...00 to the Reference Platform 16 6 2 Creating a Firmware Backup 19 6 3 Replacing the SPI 0 Contents 20 6 4 Programming a Boot Loader Firmware Image in SPI 1 21 6 4 1 If Boot Loader Image Is Less Than 8 MB 22 6 5 Booting the Example Boot Loader 22 7 Creating Custom Images 24 7 1 Edit Coreboot Image Specifications 24 7 2 Binary Configuration Tool 24 Figures Figure 1 Hardware Platform 8 Figure 2 Custo...

Page 4: ...n Revision History Date Revision Description September 2014 001 Initial release 3rd Gen Intel Core Processors with Mobile Intel HM76 QM77 Express Chipsets Platform Guide September 2014 4 Document Number 331208 001 ...

Page 5: ...oup includes but is not limited to system BIOS developers boot loader developers and system integrators 1 3 Related Documents Intel Firmware Support Package Introduction Guide available at http www intel com fsp 3rd Generation Intel Core Processor with Mobile Intel HM76 QM77 Express Chipset Integration Guide included in the corresponding FSP kit available at http www intel com fsp Binary Configura...

Page 6: ...are Support Package Application Programming Interface ME Management Engine FWG Firmware Writer s Guide PCD Platform Configuration Database PCH Platform Controller Hub SMI System Management Interrupt SMM System Management Mode SMRAM System Management RAM SPI Serial Peripheral Interface TSEG Top Segment a reserved segment of memory at the top of its address space to be used as SMRAM 3rd Gen Intel Co...

Page 7: ...The hardware platform is built on 22 nm process technology Some of the features of the hardware platform are the following Integrated graphics Low power consumption PCIe Gen 3 0 Graphics PEG port Flexible display interface Full integration of CPU GPU and memory controller Proactive security and manageability with Intel Advanced Management Technology Intel AMT 8 0 Intel Advanced Vector Extensions I...

Page 8: ...code for a specific Intel platform Engineers building systems that are based on a particular platform can integrate the corresponding FSP with the boot loader of their choice The FSP for the hardware platform handles the initialization of the processor memory and the Platform Controller Hub PCH for hardware designs based on this hardware platform 3rd Gen Intel Core Processors with Mobile Intel HM7...

Page 9: ...ial console and graphics output capabilities If you are developing a boot loader for which all user interaction is performed through the serial console use the DB 9 serial port located on the back edge of the board directly above the VGA port as illustrated in Figure 3 3rd Gen Intel Core Processors with Mobile Intel HM76 QM77 Express Chipsets September 2014 Platform Guide Document Number 331208 00...

Page 10: ...ment host system and the board The default serial communication parameters for the serial console are as follows 115 200 baud 8 N 1 bit configuration No flow control 3rd Gen Intel Core Processors with Mobile Intel HM76 QM77 Express Chipsets Platform Guide September 2014 10 Document Number 331208 001 ...

Page 11: ...irmware solution based on the Intel FSP for your hardware designs 4 1 Example Boot Loader Design The FSP s role is to initialize the processor memory and PCH The example Coreboot based boot loader calls into the FSP for these initialization steps then goes on to prepare and load a primary target that the Coreboot project calls a payload See the Coreboot project s documentation for further details ...

Page 12: ...ttp review coreboot org p coreboot This step downloads a directory named coreboot 4 Navigate into the coreboot directory 5 Run the following command to build the project specific GCC tool chain required by the Coreboot project make crossgcc i386 This command can take from a few minutes to up to an hour or more to complete depending on the power of your development host If make crossgcc i386 fails ...

Page 13: ...ract the contents of the CHIEF_RIVER_FSP_KIT_GOLD2 tgz file and follow the instructions in the Readme_Extract txt file The FSP kit will extract into a CHIEF_RIVER_FSP_KIT subfolder 3 Navigate to the CC2 directory on your development host that you created in the previous chapter Create a new subdirectory named intel parallel to the coreboot directory 4 Copy files from the CHIEF_RIVER_FSP_KIT subdir...

Page 14: ...onsole menu Navigate to the Default console log level option and set it to 4 WARNING 10 Select Exit twice to return to the command prompt Save the configuration when prompted to do so 11 Now build the boot loader with one command make 12 If the build completes without errors the newly created firmware image is generated into the following directory and file coreboot build coreboot rom The default ...

Page 15: ...an be programmed with new firmware using a DediProg SF100 programmer which is shown in Figure 4 Figure 4 SF100 Programmer The SF100 connects to a host development system through its USB plug for communication with the controller software and to obtain power it connects to the flash device to be programmed through the ISP pin header Additional technical information about the SF100 programmer includ...

Page 16: ...g instructions regarding use of the SF100 programmer assume that you have the DediProg SF100 drivers and software installed on a PC running Microsoft Windows 6 1 1 Connecting the SF100 to the Reference Platform The SF100 includes a cable shown in Figure 5 that connects between the ISP pin header and the 8 pin header labeled J2E1 on the CRB shown in Figure 6 Figure 5 DediProg Cable 3rd Gen Intel Co...

Page 17: ...Updating the Firmware Figure 6 CRB Headers and Jumpers 3rd Gen Intel Core Processors with Mobile Intel HM76 QM77 Express Chipsets September 2014 Platform Guide Document Number 331208 001 17 ...

Page 18: ...re Figure 7 shows a close up of the J2E1 header location Figure 7 J2E1 Header Location 3rd Gen Intel Core Processors with Mobile Intel HM76 QM77 Express Chipsets Platform Guide September 2014 18 Document Number 331208 001 ...

Page 19: ...he CRB at any time during this procedure 2 Connect the cable from the SF100 programmer to header J2E1 on the CRB 3 Make sure that jumpers are installed at locations J2C2 and J2D1 4 Set the jumper at J2C3 to connect pins 1 2 This step selects SPI 0 5 Open the DediProg Engineering application 6 Select W25Q64BV when prompted for the memory device type 7 In the DediProg Engineering application next to...

Page 20: ...this procedure 2 Connect the cable from the SF100 programmer to header J2E1 on the CRB 3 Make sure that jumpers are installed at locations J2C2 and J2D1 4 Set the jumper at J2C3 to connect pins 1 2 This step selects SPI 0 5 Open the DediProg Engineering application 6 Select W25Q64BV when prompted for the memory device type 7 Next to the Currently working on section near the top of the window make ...

Page 21: ...ected 9 Click the Config button at the top of the window 10 In the Advanced Settings dialog that appears click the Prog button on the left 11 Select Program a whole file starting from address 0 of a chip 12 Click the Flash Options button on the left 13 Select the check box Unprotect block automatically when block s protected 14 Click OK 15 Click the File button at the top of the window This step o...

Page 22: ...e specify a starting address of 0x0700000 6 5 Booting the Example Boot Loader By default the Coreboot based example boot loader boots into the Coreboot provided SeaBIOS The default behavior of SeaBIOS is to seek a bootable OS image on an attached storage device such as a SATA or USB disk To interact with the boot loader connect a terminal or terminal emulator to the DB 9 serial port The CRB provid...

Page 23: ...tor as determined by the configuration of the OS image If the OS image provides a graphical user interface on the VGA monitor you may need to attach a keyboard and mouse to either the USB ports or the PS 2 ports in order to fully interact with the booted operating system 3rd Gen Intel Core Processors with Mobile Intel HM76 QM77 Express Chipsets September 2014 Platform Guide Document Number 331208 ...

Page 24: ...option 5 Use the arrow keys to select the 4096 KB option 6 Select Exit twice 7 Select Yes to save your new configuration and exit the menuconfig utility 8 Back at the Coreboot directory to rebuild the coreboot rom image file type make 7 2 Binary Configuration Tool Intel provides the Binary Configuration Tool BCT that lets you edit the FSP binary file delivered with the FSP kit Use the BCT for two ...

Page 25: ...he modified settings are saved in an as built settings file absf After modifying the settings the BCT lets you patch those changes back into the binary image The BCT package is a standalone tool with its own user guide and is not dependent on a particular CPU chipset or platform Please refer to the BCT release package for further information on using this tool 3rd Gen Intel Core Processors with Mo...

Search results

Summary of Contents for Cougar Canyon 2

Reviews:

Related manuals for Cougar Canyon 2

Brands by name

Popular brands

Intel Cougar Canyon 2, Platform Manual

Search results

Summary of Contents for Cougar Canyon 2

Reviews:

Related manuals for Cougar Canyon 2

Brands by name

Popular brands