Intel CORE 2 DUO E4000 - 3-2008, Datasheet

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Electrical Specifications
26 Datasheet
NOTES:
1.
V
OS
is measured overshoot voltage.
2. T
OS
is measured time duration above VID.
2.6.4 Die Voltage Validation
Overshoot events on processor must meet the specifications in Table 8 when measured
across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in
duration may be ignored. These measurements of processor die level overshoot must
be taken with a bandwidth limited oscilloscope set to a greater than or equal to
100 MHz bandwidth limit.
2.7 Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as V
TT
. Because platforms implement
separate power planes for each processor (and chipset), separate V
CC
and V
TT
supplies
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 15 for GTLREF specifications). Termination resistors (R
TT
) for
GTL+ signals are provided on the processor silicon and are terminated to V
TT
. Intel
chipsets will also provide on-die termination, thus eliminating the need to terminate the
bus on the motherboard for most GTL+ signals.
Figure 3. V
CC
Overshoot Example Waveform
Example Overshoot Waveform
0 5 10 15 20 25
Time [us]
Volta
g
e [V]
VID - 0.000
VID + 0.050
V
OS
T
OS
T
OS
: Overshoot time above VID
V
OS
: Overshoot above VID