SRAM Configuration
The
CH-486-33A has a non-pipeline mode with a 16 bytes line
size copy-back Direct-mapped cache, because this cache
controller design two-way interleave cache read/write, so only
support 64K or 256K secondary cache size.
The following table shows the TAG RAM size, cache RAM size
and cacheable main memory size supported by CH-486-33A.
Cache size (KB)
64K
TAG RAM size
Cache
Cacheable main
RAM size
memory
8bit U34
8K x 8bit
64K x
U33
u47
32K x 8bit U34
32K x 8bit
32MB
64K x 1 bit
u47
Note .
to
cache size,
change the SRA M
TAG RAM size
Hardware Description
2-7
Summary of Contents for CH-486-33A
Page 1: ...CH 486 33A User s Manual ...
